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* glsl: allow standalone semicolons outside main()Dave Airlie2018-06-141-0/+1
| | | | | | | | | | | GLSL 4.60 offically added this but games and older CTS suites actually had shaders that did this, we may as well enable it everywhere. Adding stable because it appears apps in the wild do this. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: <[email protected]>
* radv: don't fast clear HTILE for 16-bit depth surfaces on GFX8Samuel Pitoiset2018-06-131-0/+8
| | | | | | | | | | This causes rendering issues in Shadow Warrior 2 with DXVK. Cc: [email protected] Fixes: ccc64f3133 ("radv: enable TC-compat HTILE for 16-bit depth surfaces on GFX8") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106912 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* configure.ac: Test for __atomic_add_fetch in atomic checksAndrew Galante2018-06-131-2/+4
| | | | | | | | | | Some platforms have 64-bit __atomic_load_n but not 64-bit __atomic_add_fetch, so test for both of them. Bug: https://bugs.gentoo.org/655616 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: Test for __atomic_add_fetch in atomic checksAndrew Galante2018-06-131-2/+5
| | | | | | | | | | Some platforms have 64-bit __atomic_load_n but not 64-bit __atomic_add_fetch, so test for both of them. Bug: https://bugs.gentoo.org/655616 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: Fix -latomic checkMatt Turner2018-06-131-1/+7
| | | | | | | | | | | Commit 54ba73ef102f (configure.ac/meson.build: Fix -latomic test) fixed some checks for -latomic, and then commit 54bbe600ec26 (configure.ac: rework -latomic check) further extended the fixes in configure.ac but not in Meson. This commit extends those fixes to the Meson tests. Fixes: 54bbe600ec26 (configure.ac: rework -latomic check) Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: Remove various completed todosDylan Baker2018-06-133-12/+0
| | | | | | | | v3: - Remove "won't do" todos, so only completed todo's are now removed. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]> (v2)
* meson: Make use of optional modulesDylan Baker2018-06-131-3/+12
| | | | | | | | | | | | meson 0.43 gained support for optional modules, which clover wold like to use. Since we require 0.44.1 now we can rely on them being available for clover. compile tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* meson: Add support for ppc assembly/optimizationsDylan Baker2018-06-132-4/+34
| | | | | | | | | | | v2: - Use -mpower8-vector in compiler test for altivec - rename altivec option to power8 - reword power8 option description to be more clear, originally I had made it a boolean, but replaced it with an auto option. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* meson: Add support for SPARC assemblyDylan Baker2018-06-133-2/+14
| | | | | | | | | This was blindly copied from autotools and tested by a helpful gentoo user. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* meson: Set include dirs for asmDylan Baker2018-06-131-2/+6
| | | | | | | | | v2: - split this from the next patch - Only include x86-64 and not x86 when buiding x86_64 Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* meson: move cc and cpp definitions to top of main meson.buildDylan Baker2018-06-131-2/+3
| | | | | | | | | | This just makes using cc and cpp easier. v2: - Add this patch to fix altivec Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* Revert "intel/compiler: Properly consider UBO loads that cross 32B boundaries."Jason Ekstrand2018-06-131-7/+1
| | | | | | This reverts commit b8fa847c2ed9c7c743f31e57560a09fae3992f46. This broke about 30k Vulkan CTS tests.
* intel/compiler: Properly consider UBO loads that cross 32B boundaries.Kenneth Graunke2018-06-131-1/+7
| | | | | | | | | | | | | | | | | | | The UBO push analysis pass incorrectly assumed that all values would fit within a 32B chunk, and only recorded a bit for the 32B chunk containing the starting offset. For example, if a UBO contained the following, tightly packed: vec4 a; // [0, 16) float b; // [16, 20) vec4 c; // [20, 36) then, c would start at offset 20 / 32 = 0 and end at 36 / 32 = 1, which means that we ought to record two 32B chunks in the bitfield. Similarly, dvec4s would suffer from the same problem. Reviewed-by: Rafael Antognolli <[email protected]>
* drivers/dri/i965: add missing #includeRoss Burton2018-06-121-0/+2
| | | | | | brw_bufmgr.h uses time_t without include time.h, so the build fails under musl. Reviewed-by: Eric Engestrom <[email protected]>
* anv/android: Use an address for each anv_image planeMauro Rossi2018-06-121-2/+2
| | | | | | | | | | | | | | | | | Fixes to avoid building error after change in image->planes[] structure, {bo,bo_offset} has to be replaced by address.{bo,offset} and update is needed also in the assert() for debug builds. external/mesa/src/intel/vulkan/anv_android.c:188:21: error: no member named 'bo' in 'struct anv_image::(anonymous at external/mesa/src/intel/vulkan/anv_private.h:2647:4)' image->planes[0].bo = bo; ~~~~~~~~~~~~~~~~ ^ 1 error generated. Fixes: bf34ef16ac ("anv: Use an address for each anv_image plane") Signed-off-by: Mauro Rossi <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/android: Set the BO flags in bo_cache_import (v2)Mauro Rossi2018-06-121-1/+7
| | | | | | | | | | | | | | | | | | Changes to avoid building error: external/mesa/src/intel/vulkan/anv_android.c:131:72: error: too few arguments to function call, expected 5, have 4 result = anv_bo_cache_import(device, &device->bo_cache, dma_buf, &bo); ~~~~~~~~~~~~~~~~~~~ ^ 1 error generated. (v2) Set the correct bo_flags based on support of 48bit addresses and soft-pin Fixes: b0d50247a7 ("anv/allocator: Set the BO flags in bo_cache_alloc/import") Fixes: e7d0378bd9 ("anv: Soft-pin client-allocated memory") Signed-off-by: Mauro Rossi <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Disable __gen_validate_value if NDEBUG is set.Kenneth Graunke2018-06-111-0/+2
| | | | | | | | | | | | | | | | | | We were enabling undefined memory checking for genxml values based on Valgrind being installed at build time, even for release builds. This generates piles and piles of assembly whenever you touch genxml. With gcc 7.3.1 and -O3 and -march=native on a Kabylake with Valgrind installed at build time: text data bss dec hex filename 5978385 262884 13488 6254757 5f70a5 libvulkan_intel.so 3799377 262884 13488 4075749 3e30e5 libvulkan_intel.so That's a 36% reduction in text size. Fixes: 047ed02723071d7eccbed3210b5be6ae73603a53 (vk/emit: Use valgrind to validate every packed field) Reviewed-by: Jason Ekstrand <[email protected]>
* README: wording fix for previous commitEric Engestrom2018-06-111-2/+3
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* README: add link to WhosWho for IRC nicksEric Engestrom2018-06-111-0/+2
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* add project READMEEric Engestrom2018-06-111-0/+76
| | | | | | | | | | Now that we're using GitLab, let's take advantage of the "landing page" README feature with some minimal information, mostly to point people to the right resources. Acked-by: Dylan Baker <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* i965: fix resource leakEric Engestrom2018-06-111-1/+3
| | | | | | | | | | v2: intel_miptree_release() already takes care of the planes, no need to hand-code the loop (Lionel) Coverity ID: 1436909 Fixes: 3352f2d746d3959b22ca4 "i965: Create multiple miptrees for planar YUV images" Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* freedreno/ir3: use pipe_image_view's cppRob Clark2018-06-111-1/+6
| | | | | | | At least for PIPE_BUFFER, we could get the resource used as (for example) R32F imageBuffer. So using cpp=1 from the rsc is wrong. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix image dimensions offsetRob Clark2018-06-111-1/+1
| | | | | | copy-pasta fail from how SSBO sizes are handled. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: correct image/ssbo offsetRob Clark2018-06-111-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use saml always if we have lodRob Clark2018-06-111-1/+1
| | | | | | | In some cases we get plain tex opcodes (but w/ a lod argument).. in this case always use the saml instruction. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't cp absneg into meta:fiRob Clark2018-06-111-0/+4
| | | | | | | | | | | If using a fanin (collect) to collect of consecutive registers together, we can CP mov's into the fanin, but not (abs) or (neg). No places that allow those modifiers are consuming a fanin anyways. But this caused an absneg to be lost between a ldgb and stgb for shaders like: outputs[n] = abs(input[n]) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rework size/type conversion instructionsRob Clark2018-06-111-10/+156
| | | | | | With 8b and 16b, there are a lot more to handle. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: propagate HALF flag across fanoutRob Clark2018-06-111-1/+4
| | | | | | | | | | If we have a fanout (split) meta instruction to split the result of a vector instruction, propagate the HALF flag back to the original instruction. Otherwise result ends up in a full precision register while instruction(s) that use the result look in a half-precision register. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: add sample-id/sample-mask-inRob Clark2018-06-111-3/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add sample-id/sample-mask-inRob Clark2018-06-111-0/+21
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-06-118-87/+213
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: image atomics use image-store pathRob Clark2018-06-111-0/+8
| | | | | | | | image reads are handled via tex state, whereas image writes and atomics are handled via SSBO state block. Previously we were only considering image write, and not image atomics which also uses the SSBO state block. Signed-off-by: Rob Clark <[email protected]>
* egl/glvnd: Fix a segfault in eglGetProcAddress.Kyle Brenneman2018-06-111-17/+13
| | | | | | | | | | | | If FindProcIndex in egldispatchstubs.c is called with a name that's less than the first entry in the array, it would end up trying to store an index of -1 in an unsigned integer, wrap around to 2^32, and then crash when it tries to look that up. Change FindProcIndex so that it uses bsearch(3) instead of implementing its own binary search, like the GLX equivalent FindGLXFunction does. Reviewed-by: Eric Engestrom <[email protected]>
* mesa/program_binary: add implicit UseProgram after successful ProgramBinaryJordan Justen2018-06-101-0/+31
| | | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106810 Fixes: b4c37ce2140 "i965: Add ARB_get_program_binary support using nir_serialization" Ref: 3fe8d04a6d6 "mesa: don't always set _NEW_PROGRAM when linking" Ref: c505d6d8522 "mesa: use gl_program for CurrentProgram rather than gl_shader_program" Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* features.txt: update virgl GL4.1 status.Dave Airlie2018-06-111-3/+3
| | | | | | | All the features for GL4.1 are done (64-bit attribs were part of the fp64 enable). Once tessellation shaders land this will be advertised
* virgl: enable ARB_gpu_shader_fp64Dave Airlie2018-06-112-2/+3
| | | | | | | This enables ARB_gpu_shader_fp64 if the host provides it. Tested-by: Gurchetan Singh <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* radv: add a workaround for DXVK hangs by setting amdgpu-skip-thresholdSamuel Pitoiset2018-06-091-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | Workaround for bug in llvm that causes the GPU to hang in presence of nested loops because there is an exec mask issue. The proper solution is to fix LLVM but this might require a bunch of work. This fixes a bunch of GPU hangs that happen with DXVK. Vega10: Totals from affected shaders: SGPRS: 110456 -> 110456 (0.00 %) VGPRS: 122800 -> 122800 (0.00 %) Spilled SGPRs: 7478 -> 7478 (0.00 %) Spilled VGPRs: 36 -> 36 (0.00 %) Code Size: 9901104 -> 9922928 (0.22 %) bytes Max Waves: 7143 -> 7143 (0.00 %) Code size slightly increases because it inserts more branch instructions but that's expected. I don't see any real performance changes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105613 Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix missing ZRANGE_PRECISION(1) for GFX9+Samuel Pitoiset2018-06-091-1/+2
| | | | | | | | | | | | | | | ZRANGE_PRECISION(1) seems to be the default optimal value, but it was only set for VI and older chips. This fixes a rendering issue with Banished through DXVK, and might fix more than that. There is still the ZRANGE_PRECISION bug that we need to handle but that can be fixed later. Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv: enable VK_EXT_shader_stencil_exportGustavo Lima Chaves2018-06-083-0/+3
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add/hookup SpvCapabilityStencilExportEXTGustavo Lima Chaves2018-06-083-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior also follows, with the interpretation to said mode being we prevent writes to the built-in FragStencilRefEXT variable when the execution mode isn't set. v3: A more cautious reading of 1db44252d01bf7539452ccc2b5210c74b8dcd573 led me to a missing change that would stop (what I later discovered were) GPU hangs on the CTS test written to exercise this. v4: Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT mode into a warning, instead of trying to make the variable read-only. If we are to follow the originating extension on GL, the built-in variable in question should never be readable anyway. v5/v6: rebases. v7: Fix check for gen9 lost in rebase. (Ilia) Reduce the scope of the bool used to track whether SpvExecutionModeStencilRefReplacingEXT was used. Was in shader_info, moved to vtn_builder. (Jason) v8: Assert for fragment shader handling StencilRefReplacingEXT execution mode. (Caio) Remove warning logic, since an entry point might not have StencilRefReplacingEXT execution mode, but the global output variable might still exist for another entry point in the module. (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* travis: Add the v3d driver to the automake build.Eric Anholt2018-06-081-1/+1
| | | | | | | | Hopefully this reduces the number of fixup commits we need for the automake build. Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* travis: Do our automake build tests with srcdir != builddir.Eric Anholt2018-06-081-1/+3
| | | | | | | | This will catch many automake bugs that end-users get to experience first, otherwise. Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* autotools/meson: compile against wayland-egl-*backend*Eric Engestrom2018-06-083-4/+6
| | | | | | | | Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106861 Fixes: 1db4ec05462914096b1f "egl: rewire the build systems to use libwayland-egl" Suggested-by: Emil Velikov <[email protected]> Tested-by: Andreas Hartmetz <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* vulkan/wsi: Destroy swapchain images after terminating FIFO queuesCameron Kumar2018-06-081-3/+3
| | | | | | | | | The queue_manager thread can access the images from x11_present_to_x11, hence this reorder prevents dereferencing of dangling pointers. Cc: "18.1" <[email protected]> Fixes: e73d136a023080 ("vulkan/wsi/x11: Implement FIFO mode.") Reviewed-by: Lionel Landwerlin <[email protected]>
* radeonsi: emit_dpbb_state packets optimizationSonny Jiang2018-06-072-21/+26
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_clip_state packets optimizationSonny Jiang2018-06-072-3/+7
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_msaa_sample_locs packets optimizationSonny Jiang2018-06-072-2/+6
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_msaa_config packets optimizationSonny Jiang2018-06-072-28/+28
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_cb_render_state packets optimizationSonny Jiang2018-06-073-9/+48
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_db_render_state packets optimizationSonny Jiang2018-06-075-29/+95
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
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