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* i965: Move SF compilation to the compilerJason Ekstrand2017-05-2610-246/+209
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/clip: Make brw_clip_prog_key::interp_mode an arrayJason Ekstrand2017-05-262-2/+6
| | | | | | | | | Having it be a pointer means that we end up caching clip programs based on a pointer to wm_prog_data rather than the actual interpolation modes. We've been caching one clip program per FS ever since 91d61fbf7cb61a44a where Timothy rewrote brw_setup_vue_interpolation(). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/sf: make brw_sf_prog_key::interp_mode an arrayJason Ekstrand2017-05-262-2/+6
| | | | | | | | | Having it be a pointer means that we end up caching clip programs based on a pointer to wm_prog_data rather than the actual interpolation modes. We've been caching one clip program per FS ever since 91d61fbf7cb61a44a where Timothy rewrote brw_setup_vue_interpolation(). Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/compiler: Make brw_disasm take const assemblyJason Ekstrand2017-05-263-15/+15
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/decoder: Handle the BLT ring in gen_group_get_lengthJason Ekstrand2017-05-261-0/+4
| | | | Reviewed-by: Jordan Justen <[email protected]>
* intel/decoder: Handle gen4 VF_STATISTICS and PIPELINE_SELECTJason Ekstrand2017-05-261-2/+7
| | | | | | | These need special handling because they have no "DWord Length" parameter and they have an unusual bias of 1. Reviewed-by: Jordan Justen <[email protected]>
* intel/genxml: Rename 3DSTATE_AA_LINE_PARAMS on gen5Jason Ekstrand2017-05-261-1/+1
| | | | | | All of the other gens use "PARAMETERS". Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Use the right subtype for VF_STATISTICS on gen4Jason Ekstrand2017-05-261-1/+1
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Iron Lake doesn't support non-normalized sampler coordinatesJason Ekstrand2017-05-261-1/+0
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Add SAMPLER_STATE to gen 4.5Jason Ekstrand2017-05-261-0/+63
| | | | | | Somehow this got missed. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Rename the CC_VIEWPORT pointer on gen4-5Jason Ekstrand2017-05-263-3/+3
| | | | | | | It isn't a pointer to "color calc state", that's the packet it's in. It's a pointer to the CC viewport state. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Sampler state is a pointer on gen4-5Jason Ekstrand2017-05-264-10/+10
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Suffix KSP0 fields on Iron LakeJason Ekstrand2017-05-261-5/+5
| | | | | | | | | Iron Lake introduced the multiple KSP thing and so you have KSP0-3. However, the genxml didn't have an index on the first "Kernel Start Pointer" or "GRF Register Count". Add one to match gen6+. While we're here, we drop the brackets from the other "GRF Register Count" fields. Reviewed-by: Matt Turner <[email protected]>
* intel/genxml: Make a bunch of things offsets on gen4-5Jason Ekstrand2017-05-263-15/+15
| | | | | | | | | Most things on gen4-5 are addresses because we don't have dynamic state base address and we don't have instruction state base on gen4. However, whoever converted things to addresses got a little over-excited and converted too much. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add gen4_filter_tilingJason Ekstrand2017-05-263-2/+57
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for setting component write disablesJason Ekstrand2017-05-262-0/+26
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for gen4 cube maps to get_image_offset_saJason Ekstrand2017-05-261-5/+18
| | | | | | | Gen4 cube maps are a 2-D surface with ISL_DIM_LAYOUT_GEN4_3D which is a bit weird but accurate none the less. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Don't request space for stencil/hiz packets unless neededJason Ekstrand2017-05-261-7/+6
| | | | | | | On Iron Lake, the packets exist but we never emit them so there's no need for us to ask the driver to make batch space for them. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Properly handle mt->first_levelJason Ekstrand2017-05-261-0/+3
| | | | | | | | The guts of blorp and ISL don't understand i965's partial miptrees. Instead, we need to subtract off first_level before we hand anything off to blorp. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Take first_level into account when converting to ISLJason Ekstrand2017-05-261-1/+1
| | | | | | | ISL doesn't have a concept of a partial miptree. Instead, we need to subtract off first_level. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Move the gen7 stencil format workaround to blorp_blitJason Ekstrand2017-05-262-5/+9
| | | | | | | | It's not needed for blorp_copy because it already overrides formats. It's also not needed for blorp_clear because it clears stencil as stencil. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use blorp_copy for doing r8 stencil updates on HSWJason Ekstrand2017-05-261-15/+4
| | | | | | | | | | The blorp_copy entrypoint is designed for doing memcpy like operations which is what we need to do here while blorp_blit is for handling format conversion and scaling. Using blorp_copy is much simpler and prevents us from getting formats wrong. While we're here, we get rid of the layers_per_blit thing since stencil always uses interleaved MSAA. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Do and end-of-pipe sync on both sides of fast-clear opsJason Ekstrand2017-05-261-18/+38
| | | | | | | | | | | | | | | | We've discovered in the Vulkan driver that simply doing the end-of-pipe sync afterwards is insufficient. The specific requirement stated in the PRM is that you have to do one every time you transition between the tree modes of "clear", "render", and "resolve". This is GL, so we could track it but any attempt to do so would most likely get it wrong. For now, it's easier to just assume that every fast-clear op is an island and do the sync both before and after. This also removes the unneeded flush and stall after slow-clear operations. Reviewed-by: Topi Pohjolainen <[email protected]> Cc: "17.0 17.1" <[email protected]>
* amd/common: add missing libdrm include pathEric Engestrom2017-05-261-0/+1
| | | | | | Fixes: de9dd4f9f1bb5984c554 ("ac/radeonsi: move struct radeon_info to ac_gpu_info.h") Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* docs: small release calendar fixesAndres Gomez2017-05-262-2/+2
| | | | | Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* Revert "amd/common: add vcn dec ip info query"Dave Airlie2017-05-261-7/+1
| | | | | | | | This reverts commit 524d4fff9e0e58e812e71bc5ba2c92ffa73bee16. This commit breaks amdgpu on kernels with no DEC IP support. Caught by the airlied CI system.
* Revert "amd/common: set vcn dec as hw decode as well"Dave Airlie2017-05-261-2/+0
| | | | | | | This reverts commit 50d322be2f30bb935ee52b3b3649785975771110. A previous patch breaks amdgpu on non-vcn decode systems, but have to revert this first.
* util: remove unneeded Android ifdef from ralloc.cRob Herring2017-05-251-5/+0
| | | | | | | | | SIZE_MAX has been defined in stdint.h on Android since 2013, so this ifdef is no longer needed. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* nouveau: drop Android 4.4 and earlier supportRob Herring2017-05-252-33/+3
| | | | | | | | | Support for Android 4.4 and earlier has already been removed from mesa. Remove this remaining piece from nouveau, too. Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* i965: use mmap64 for AndroidRob Herring2017-05-251-16/+3
| | | | | | | | | Simplify the handling of mmap for Android by using mmap64 instead. mmap64 may have not existed for Android when this was written, but it's been around since 2013. Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* gallium/os: use mmap64 for AndroidRob Herring2017-05-251-18/+3
| | | | | | | | | Simplify the handling of mmap for Android by using mmap64 instead. mmap64 may have not existed for Android when this was written, but it's been around since 2013. Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* Android: generate an error if building on Android 4.4 or earlierRob Herring2017-05-251-0/+3
| | | | | | | | | Since commit 7a5b5f52260 ("Android: drop Android 4.4 (KitKat) support"), Android 4.4 or earlier is no longer supported, so exit with an error if we try building on it. Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* st/wgl: whitespace, formatting fixes in stw_device.cBrian Paul2017-05-251-12/+9
| | | | Trivial.
* glsl: Fix g++ initializer order warningBrian Paul2017-05-251-1/+1
| | | | | | | | | | | | | | | | | Fixes this warning: In file included from ../../../src/compiler/glsl/ir.cpp:25:0: ../../../src/compiler/glsl/ir.h: In constructor 'ir_swizzle::ir_swizzle(ir_rvalue*, ir_swizzle_mask)': ../../../src/compiler/glsl/ir.h:1955:20: warning: 'ir_swizzle::mask' will be initialized after [-Wreorder] ir_swizzle_mask mask; ^ ../../../src/compiler/glsl/ir.h:1954:15: warning: 'ir_rvalue* ir_swizzle::val' [-Wreorder] ir_rvalue *val; ^ ../../../src/compiler/glsl/ir.cpp:1592:1: warning: when initialized here [-Wreorder] ir_swizzle::ir_swizzle(ir_rvalue *val, ir_swizzle_mask mask) ^ Reviewed-by: Matt Turner <[email protected]>
* radeonsi: enable vcn decodeLeo Liu2017-05-251-1/+4
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* winsys/amdgpu: add vcn dec cs supportLeo Liu2017-05-251-1/+10
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* amd/common: set vcn dec as hw decode as wellLeo Liu2017-05-251-0/+2
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* amd/common: add vcn dec ip info queryLeo Liu2017-05-251-1/+7
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon: rename has_uvd info to has_hw_decodeLeo Liu2017-05-256-8/+8
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add decode message for mpeg4 codecLeo Liu2017-05-251-0/+51
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add decode message for mpeg2 codecLeo Liu2017-05-251-0/+66
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add decode message for vc1 codecLeo Liu2017-05-251-0/+72
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add decode message for hevc codecLeo Liu2017-05-251-0/+225
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add decode message decode for avc codecLeo Liu2017-05-251-4/+193
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add decode message feedbackLeo Liu2017-05-251-1/+5
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add decode message destroyLeo Liu2017-05-251-1/+10
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add decode message createLeo Liu2017-05-251-1/+21
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add common decode partLeo Liu2017-05-253-0/+675
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/winsys: add vcn dec ring typeLeo Liu2017-05-251-0/+1
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/winsys: add uvd enc ring typeLeo Liu2017-05-251-0/+1
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
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