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* winsys/amdgpu: init buffer_indices_hashlist with memset()Samuel Pitoiset2017-04-171-8/+2
* winsys/amdgpu: simplify amdgpu_cs_add_buffer() a bitSamuel Pitoiset2017-04-171-4/+3
* i965/drm: Delete NULL check in brw_bo_unmap().Kenneth Graunke2017-04-161-3/+0
* intel/decoder: Fix is_header_field starting condition.Kenneth Graunke2017-04-161-1/+1
* i965/drm: Remove dead return in brw_bo_busy()Kenneth Graunke2017-04-161-3/+1
* android: amd/addrlib: trivial fix for gfx9 supportMauro Rossi2017-04-171-0/+2
* nir: Add GLSL_TYPE_[U]INT64 to some switch statementsJason Ekstrand2017-04-162-0/+4
* gallium/radeon: always flush asynchronously and wait after begin_new_csMarek Olšák2017-04-172-4/+11
* radeonsi: remove local variable 'mod' from si_compile_tgsi_shaderMarek Olšák2017-04-171-5/+2
* radeonsi: add si_shader_selector::vs_needs_prologMarek Olšák2017-04-173-7/+10
* radeonsi: don't set VGT_GS_MODE as part of the GS stateMarek Olšák2017-04-171-2/+0
* radeonsi: don't allow user indices with indirect drawsMarek Olšák2017-04-171-4/+4
* radeonsi: merge two if (indirect) statementsMarek Olšák2017-04-171-27/+25
* radeonsi: don't mark non-dirty textures with CMASK as compressedMarek Olšák2017-04-171-2/+3
* docs: Document interaction Fixes tag and stable branches.Bas Nieuwenhuizen2017-04-151-0/+4
* glsl: don't run the GLSL pre-processor when we are skipping compilationTimothy Arceri2017-04-152-9/+20
* glsl: delay optimisations on individual shaders when cache is availableTimothy Arceri2017-04-154-78/+96
* anv: Add the pci_id into the shader cache UUIDJason Ekstrand2017-04-141-5/+15
* etnaviv: native fence fd supportPhilipp Zabel2017-04-157-7/+83
* docs: mark GL_ARB_vertex_attrib_64bit and OpenGL 4.2 as supported by i965/gen7+Francisco Jerez2017-04-142-4/+7
* i965: enable OpenGL 4.2 in IvybridgeJuan A. Suarez Romero2017-04-142-2/+2
* i965: enable ARB_shader_precision in gen7+Samuel Iglesias Gonsálvez2017-04-141-1/+1
* i965: enable ARB_vertex_attrib_64bit for gen7+Juan A. Suarez Romero2017-04-141-1/+1
* swr: Fix swr osmesa buildGeorge Kyriazis2017-04-141-1/+1
* etnaviv: SINGLE_BUFFER support on GC3000Wladimir J. van der Laan2017-04-158-28/+63
* etnaviv: Update includes from rnndbWladimir J. van der Laan2017-04-155-20/+91
* etnaviv: Add chipMinorFeatures4 and 5Wladimir J. van der Laan2017-04-152-1/+15
* etnaviv: resolve tile status when flushing resourcePhilipp Zabel2017-04-152-0/+11
* etnaviv: stop repeatedly resolving an unchanged resource into its scanout pri...Philipp Zabel2017-04-151-1/+4
* swr: Add polygon stipple supportGeorge Kyriazis2017-04-145-9/+84
* docs/relnotes: add GL_ARB_gpu_shader_fp64 support on i965/ivybridgeSamuel Iglesias Gonsálvez2017-04-141-0/+1
* docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+Samuel Iglesias Gonsálvez2017-04-141-2/+2
* i965: enable OpenGL 4.0 to Ivybridge/BaytrailSamuel Iglesias Gonsálvez2017-04-142-5/+6
* i965: enable ARB_gpu_shader_fp64 for Ivybridge/BaytrailSamuel Iglesias Gonsálvez2017-04-141-1/+1
* i965: Use correct VertStride on align16 instructions.Matt Turner2017-04-141-10/+34
* i965/vec4/dce: improve track of partial flag register writesSamuel Iglesias Gonsálvez2017-04-141-1/+1
* i965/vec4: don't do horizontal stride on some register file typesSamuel Iglesias Gonsálvez2017-04-141-2/+5
* i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT.Matt Turner2017-04-141-4/+12
* i965/vec4: use vec4_builder to emit instructions in setup_imm_df()Samuel Iglesias Gonsálvez2017-04-142-50/+50
* i965/vec4: consider subregister offset in live variablesJuan A. Suarez Romero2017-04-141-2/+2
* i965/vec4: fix assert to detect SIMD lowered DF instructions in IVBFrancisco Jerez2017-04-141-5/+1
* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-147-27/+60
* i965/vec4: split d2x conversion and data gathering from one opcode to two exp...Samuel Iglesias Gonsálvez2017-04-142-8/+1
* i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYTJuan A. Suarez Romero2017-04-141-7/+19
* i965/vec4: keep original type when dealing with null registersJuan A. Suarez Romero2017-04-141-0/+2
* i965/vec4: split DF instructions and later double its execsize in IVB/BYTSamuel Iglesias Gonsálvez2017-04-143-1/+53
* i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYTSamuel Iglesias Gonsálvez2017-04-141-0/+9
* i965/fs: Get 64-bit indirect moves working on IVB.Francisco Jerez2017-04-141-2/+25
* i965: Use source region <1,2,0> when converting to DF.Matt Turner2017-04-142-13/+28
* i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECTJuan A. Suarez Romero2017-04-141-3/+14
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