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* draw: whitespace fixes in draw_pipe_vbuf.cBrian Paul2017-04-261-104/+89
| | | | Remove trailing whitespace, fix formatting, etc. Trivial.
* st/mesa: minor clean-ups in st_update_renderbuffer_surface()Brian Paul2017-04-261-9/+8
| | | | | | | | Remove unneeded parens. Add const qualifiers. Move var decls closer to where they're used. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Neha Bhende<[email protected]>
* nv50,nvc0: disable the TGSI merge registers passSamuel Pitoiset2017-04-262-2/+4
| | | | | | | | | | | | | | | | shader-db results on GK106 (Thanks Karol): total instructions in shared programs : 3931608 -> 3929463 (-0.05%) total gprs used in shared programs : 481255 -> 479014 (-0.47%) total local used in shared programs : 27481 -> 27381 (-0.36%) total bytes used in shared programs : 36031256 -> 36011120 (-0.06%) local gpr inst bytes helped 14 1471 1309 1309 hurt 1 88 384 384 Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* radeonsi: disable the TGSI merge registers passSamuel Pitoiset2017-04-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 47109 shaders in 29632 tests Totals: SGPRS: 1917364 -> 1916620 (-0.04 %) VGPRS: 1165802 -> 1165202 (-0.05 %) Spilled SGPRs: 1880 -> 1843 (-1.97 %) Spilled VGPRs: 70 -> 65 (-7.14 %) Private memory VGPRs: 1184 -> 1184 (0.00 %) Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread Code Size: 60211356 -> 60192268 (-0.03 %) bytes LDS: 1077 -> 1077 (0.00 %) blocks Max Waves: 428597 -> 428674 (0.02 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 238173 -> 237429 (-0.31 %) VGPRS: 149556 -> 148956 (-0.40 %) Spilled SGPRs: 1263 -> 1226 (-2.93 %) Spilled VGPRs: 25 -> 20 (-20.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 20 -> 16 (-20.00 %) dwords per thread Code Size: 10457904 -> 10438816 (-0.18 %) bytes LDS: 50 -> 50 (0.00 %) blocks Max Waves: 41283 -> 41360 (0.19 %) Wait states: 0 -> 0 (0.00 %) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_tgsi: disable the merge registers pass conditionallySamuel Pitoiset2017-04-261-1/+6
| | | | | | | | | | | | | | | | | | | | | The main goal of this pass to merge temporary registers in order to reduce the total number of registers and also to produce optimal TGSI code. In fact, compilers seem to be confused when temporary variables are already merged, maybe because it's done too early in the process. Skipping the pass, reduce both the register pressure and the code size, at least for Nouveau and RadeonSI because they have a real backend compiler. Found by luck while fixing an issue in the TGSI dead code elimination pass which affects tex instructions with bindless samplers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERSSamuel Pitoiset2017-04-2615-0/+21
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use unsynchronized transfers for shader binary uploadsSamuel Pitoiset2017-04-261-1/+2
| | | | | | | | | | | Because the buffer is new, it can't be referenced by any CS. This can save few CPU cycles by skipping the whole PIPE_TRANSFER_UNSYNCHRONIZED if in amdgpu_bo_map(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: turn si_shader_key::mono into a non-unionMarek Olšák2017-04-263-15/+11
| | | | | | | A merged LS-HS shader needs both fix_fetch and inputs_to_copy for compilation. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: adjust ESGS ring buffer size computation on VIMarek Olšák2017-04-261-1/+4
| | | | | Cc: 17.0 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't set deprecated field PARTIAL_ES_WAVE_ONMarek Olšák2017-04-261-2/+3
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct registerMarek Olšák2017-04-262-1/+5
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add a workaround for viewing a slice of 3D as a 2D imageMarek Olšák2017-04-261-8/+22
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix 1D array shader imagesMarek Olšák2017-04-261-0/+1
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix most things wrong with shader imagesMarek Olšák2017-04-262-12/+24
| | | | | | | | | | | | There are 2 major hw changes: - The address must always point to the address of level 0. GFX9 tiling modes don't allow binding to a non-0 level. - 3D must always be bound as 3D, because 2D and 3D use entirely different tiling modes, and the texture target determines which set of modes is used. Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix texture buffer objects and image buffers with IDXEN==0Marek Olšák2017-04-261-1/+34
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* configure: print LDFLAGS alongside CFLAGS & co.Eric Engestrom2017-04-261-1/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: tidy up left over APPLE_vertex_array_object semanticsTimothy Arceri2017-04-264-43/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: inline bind_vertex_array() helperTimothy Arceri2017-04-261-17/+6
| | | | | | The previous commit removed the only other user of this function. Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: drop APPLE_vertex_array_object supportTimothy Arceri2017-04-2612-101/+20
| | | | | | | | | | | | | | | | | | | | | Shared context support for VAOs was dropped in 0b2750620b65. From the ARB_vertex_array_object spec: "This extension differs from GL_APPLE_vertex_array_object in that client memory cannot be accessed through a non-zero vertex array object. It also differs in that vertex array objects are explicitly not sharable between contexts." Nobody should be using this extension over ARB_vertex_array_object anymore so just drop it rather than adding locking back just for VAOs created from these functions. For reference the Nvidia blob doesn't expose this extension. Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Enable userspace fence checking.Bas Nieuwenhuizen2017-04-263-3/+36
| | | | | | | | | | v2: - Added some error handling. - memset the buffer to 0. v3: Added assert for buffer size. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* i965: Remove unused variable 'options'Matt Turner2017-04-251-2/+0
| | | | Should have been removed in commit ad55b1a7701a
* glsl: Initialize current_varMatt Turner2017-04-251-1/+1
| | | | CID: 1324644 (Uninitialized pointer field)
* radv/ac: setup mrt exports then export them in one go. (v2)Dave Airlie2017-04-251-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Noticed while looking at Sascha Willems deferred shaders. This is a bit of an llvm workaround, llvm was producing this: v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ; D2960004 00021107 v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ; D2960006 0001E509 s_waitcnt vmcnt(0) ; BF8C0F70 exp mrt0 v4, v4, v6, v6 compr ; C400040F 00000604 s_waitcnt expcnt(0) ; BF8C0F0F v_cvt_pkrtz_f16_f32_e64 v4, v12, v5 ; D2960004 00020B0C v_cvt_pkrtz_f16_f32_e64 v5, v14, 1.0 ; D2960005 0001E50E exp mrt1 v4, v4, v5, v5 compr ; C400041F 00000504 s_waitcnt expcnt(0) ; BF8C0F0F v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp mrt2 v0, v0, v1, v1 done compr vm ; C4001C2F 00000100 After this change: v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ; D2960004 00021107 s_waitcnt vmcnt(0) ; BF8C0F70 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ; D2960006 0001E509 v_cvt_pkrtz_f16_f32_e64 v5, v12, v5 ; D2960005 00020B0C v_cvt_pkrtz_f16_f32_e64 v7, v14, 1.0 ; D2960007 0001E50E exp mrt0 v4, v4, v6, v6 compr ; C400040F 00000604 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp mrt1 v5, v5, v7, v7 compr ; C400041F 00000705 exp mrt2 v0, v0, v1, v1 done compr vm ; C4001C2F 00000100 No waitcnt for exports are emitted. v2: fixup index->mrt mapping (Bas). Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: overhaul vs output/ps input routingDave Airlie2017-04-253-37/+55
| | | | | | | | In order to cleanly eliminate exports rewrite the code first to mirror how radeonsi works for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: move point coord after layer/viewport.Dave Airlie2017-04-251-6/+7
| | | | | | | | These need to be ordered as per shader enum ordering, I'll rewrite this soon, but this is a bug fix. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: remove u_caps.c/h interfaceSamuel Pitoiset2017-04-253-340/+0
| | | | | | | No longer used. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: implement get_query_result_resourceMarek Olšák2017-04-251-0/+16
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* trace: don't trace resource_destroyMarek Olšák2017-04-251-7/+4
| | | | | | | due to the lack of pipe_resource wrapping, we can get this call from inside of driver calls, which would try to lock an already-locked mutex. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/util: add debugging helpers printing pipeline statisticsMarek Olšák2017-04-252-0/+59
| | | | | | typically useful for hw bring-up Reviewed-by: Nicolai Hähnle <[email protected]>
* Android: fix r300g only buildRob Herring2017-04-251-3/+5
| | | | | | | | | | | | | | | | | | | | If r300g is the only radeon driver built, the Android build fails to build: ninja: error: 'out/target/product/linaro_x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeon_intermediates/export_includes', needed by 'out/target/product/linaro_x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/import_includes', missing and no known rule to make it This is because the path to build libmesa_pipe_radeon was only getting added for r600g and radeonsi, but the library dependency was added for all radeon drivers. As libmesa_pipe_radeon is not needed for r300g, drop the library dependency. Cc: Mauro Rossi <[email protected]> Signed-off-by: Rob Herring <[email protected]> Acked-by: Emil Velikov <[email protected]>
* mesa: use locked version of HashWalk for xfb objectsTimothy Arceri2017-04-251-2/+2
| | | | | | | | | | | | From Chapter 5 'Shared Objects and Multiple Contexts' of the OpenGL 4.5 spec: "Objects which contain references to other objects include framebuffer, program pipeline, query, transform feedback, and vertex array objects. Such objects are called container objects and are not shared" Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: create locked version of HashWalkTimothy Arceri2017-04-252-8/+31
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* genxml: Fix gen_pack_header.py crash when field type is invalid.Rafael Antognolli2017-04-241-2/+2
| | | | | | | | Just return earlier in that case. Also set prefix to an empty string, so we don't get to use it undefined. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make BLEND_STATE command support variable length array.Rafael Antognolli2017-04-247-48/+74
| | | | | | | | | | | | | | | | | | | | | | | | We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers dwords (on gen8+), but the BLEND_STATE struct length is always 17. By marking it size 1, which is actually the size of the struct minus the BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of entries. For gen6 and gen7 we set length to 0, since it only contains BLEND_STATE_ENTRY's, and no other data. With this change, we also change the code for blorp and anv to emit only the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on gen6-7 and 17 dwords on gen8+. v2: - Use designated initializers on blorp and remove 0 from initialization (Jason) - Default entries to disabled on Vulkan (Jason) - Rebase code. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Fix python crash when no dwords are found.Rafael Antognolli2017-04-241-5/+12
| | | | | | | | | | | | | | | If the 'dwords' dict is empty, max(dwords.keys()) throws an exception. This case could happen when we have an instruction that is only an array of other structs, with variable length. v2: - Add another clause for empty dwords and make it work with python 3 (Dylan) - Set the length to 0 if dwords is empty, and do not declare dw Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Remove unused parameter.Rafael Antognolli2017-04-241-2/+2
| | | | | | | 'start' parameter from Group.emit_pack_function() is useless. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/aubinator: Correctly read variable length structs.Rafael Antognolli2017-04-243-6/+54
| | | | | | | | | | | | | | | | Before this commit, when a group with count="0" is found, only one field is added to the struct representing the instruction. This causes only one entry to be printed by aubinator, for variable length groups. With this commit we "detect" that there's a variable length group (count="0") and store the offset of the last entry added to the struct when reading the xml. When finally reading the aubdump file, we check the size of the group and whether we have variable number of elements, and in that case, reuse the last field to add the remaining elements. Signed-off-by: Rafael Antognolli <[email protected]> Tested-by: Jason Ekstrand <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* isl/format: Update the R16G16B16X16_FLOAT entryNanley Chery2017-04-241-1/+1
| | | | | | | | | | | The section of the PRM mentioned in the code comment above this table says that this format supports the render target write message. Internal documentation says that this format also supports alpha blending. As a side effect, this allows CCS_D buffers to be created for images with this format. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* anv/pass: Delete anv_pass::subpass_attachmentsNanley Chery2017-04-241-1/+0
| | | | | | | This field has no users. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* intel/fs: Take into account amount of data read in spilling cost heuristic.Francisco Jerez2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | Until now the spilling cost calculation was neglecting the amount of data read from the register during the spilling cost calculation. This caused it to make suboptimal decisions in some cases leading to higher memory bandwidth usage than necessary. Improves Unigine Heaven performance by ~4% on BDW, reversing an unintended FPS regression from my previous commit 147e71242ce539ff28e282f009c332818c35f5ac with n=12 and statistical significance 5%. In addition SynMark2 OglCSDof performance is improved by an additional ~5% on SKL, and a Kerbal Space Program apitrace around the Moho planet I can provide on request improves by ~20%. Cc: <[email protected]> Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Use regs_written() in spilling cost heuristic for improved accuracy.Francisco Jerez2017-04-241-2/+1
| | | | | | | | | | This is what we use later on to compute the number of registers that will actually get spilled to memory, so it's more likely to match reality than the current open-coded approximation. Cc: <[email protected]> Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Use reads_accumulator_implicitly(), not MACH checks.Kenneth Graunke2017-04-241-4/+4
| | | | | | | | | Curro pointed out that I should not just check for MACH, but use the reads_accumulator_implicitly() helper, which would also prevent the same bug with MAC and SADA2 (if we ever decide to use them). Cc: [email protected] Reviewed-by: Francisco Jerez <[email protected]>
* android: radv/ac: Fix nir.h includeMauro Rossi2017-04-241-0/+2
| | | | | | | | | | | | | | Fixes following building errors due to missing include paths: external/mesa/src/amd/common/ac_shader_info.c:23:10: fatal error: 'nir/nir.h' file not found ^ external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found ^ Fixes: 224cf29 "radv/ac: add initial pre-pass for shader info gathering" Acked-by: Dave Airlie <[email protected]> Acked-by: Emil Velikov <[email protected]>
* configure.ac: Fix typos.Vinson Lee2017-04-231-3/+3
| | | | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Cc: <[email protected]>
* radv/ac: copy llvm machine feature flags from radeonsi.Dave Airlie2017-04-241-1/+1
| | | | | | | | This just updates this to use the same flags as radeonsi for consistency. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: remove now unused GLSL IR optimisationsTimothy Arceri2017-04-244-888/+0
| | | | | | | These are no longer used since the previous commit. Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: remove GLSL IR optimisation loopTimothy Arceri2017-04-241-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IVB is running into some spilling issues in piglit with the loop removed. However those tests are not really reflective of a real world use case, also fp64 is brand new to IVB so we leave the spilling issues to be resolved at a later time. Run time for shader-db on my machine goes from ~795 seconds to ~665 seconds. shader-db results BDW: total instructions in shared programs: 12969459 -> 12968891 (-0.00%) instructions in affected programs: 1463154 -> 1462586 (-0.04%) helped: 3622 HURT: 3326 total cycles in shared programs: 246453572 -> 246504318 (0.02%) cycles in affected programs: 208842622 -> 208893368 (0.02%) helped: 24029 HURT: 35407 total loops in shared programs: 2931 -> 2931 (0.00%) loops in affected programs: 0 -> 0 helped: 0 HURT: 0 total spills in shared programs: 14560 -> 14498 (-0.43%) spills in affected programs: 2270 -> 2208 (-2.73%) helped: 17 HURT: 2 total fills in shared programs: 19671 -> 19632 (-0.20%) fills in affected programs: 2060 -> 2021 (-1.89%) helped: 17 HURT: 2 LOST: 17 GAINED: 40 Most of the hurt shaders are 1-2 instructions, with what looks like a max of 7. I've looked at the worst cycles regressions and as far as I can tell its just a scheduling difference. Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: use ARB_enhahnced_layouts for packing where possibleTimothy Arceri2017-04-241-0/+70
| | | | | | | | | | | | | | | | | | | | | If packing doesn't cross locations we can easily make use of ARB_enhanced_layouts to do packing rather than using the GLSL IR lowering pass lower_packed_varyings(). Shader-db Broadwell results: total instructions in shared programs: 12977822 -> 12977819 (-0.00%) instructions in affected programs: 1871 -> 1868 (-0.16%) helped: 4 HURT: 3 total cycles in shared programs: 246567288 -> 246567668 (0.00%) cycles in affected programs: 1370386 -> 1370766 (0.03%) helped: 592 HURT: 733 Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: disable varying packing for varying used by interpolateAt*Timothy Arceri2017-04-243-7/+19
| | | | | | | | | | | | | | | | | Currently the NIR backends depend on GLSL IR copy propagation to fix up the interpolateAt* function params after varying packing changes the shader input to a global. It's possible copy propagation might not always do what we need it too, and we also shouldn't depend on optimisations to do this type of thing for us. I'm not sure if the same is true for TGSI, but the following commit should re-enable packing for most cases in a safer way, so we just disable it everywhere. No change in shader-db for i965 (BDW) Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_to_nir: skip ir_var_shader_shared variablesTimothy Arceri2017-04-241-0/+7
| | | | | | | | | | | | | | These should be lowered away in GLSL IR but if we don't get dead code to clean them up it causes issues in glsl_to_nir. We wan't to drop as many GLSL IR opts in future as we can so this makes glsl_to_nir just ignore the vars if it sees them. In future we will want to just use the nir lowering pass that Vulkan currently uses. Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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