summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* dri/swrast: add GLX_MESA_query_renderer supportEmil Velikov2014-08-151-2/+71
| | | | | | | | | v2: - Drop __DRI2_RENDERER_PREFERRED_PROFILE case. - Cleanup return statements. Cc: Brian Paul <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* dri/radeon: add GLX_MESA_query_renderer supportEmil Velikov2014-08-154-21/+103
| | | | | | | | | | - Create radeon{Vendor,GetRenderer}String helpers. - Drop __DRI2_RENDERER_PREFERRED_PROFILE case. - Cleanup return statements. To be used by the upcomming GLX_MESA_query_renderer implementation. Signed-off-by: Emil Velikov <[email protected]>
* dri/radeon: don't print TCL status on glGetString(GL_RENDERER)Emil Velikov2014-08-151-7/+2
| | | | | | | | | | Printing the TCL involves that context is available at the time of query. The GLX_MESA_query_renderer states that glGetString(GL_RENDERER) and glXQueryRendererStringMESA(GLX_RENDERER_DEVICE_ID_MESA) will have the same format, thus removing the context dependenicy will help us achieve that. Signed-off-by: Emil Velikov <[email protected]>
* dri/nouveau: add GLX_MESA_query_renderer supportEmil Velikov2014-08-153-19/+92
| | | | | | | | - Create nouveau_{vendor,get_renderer}_string helpers. - Set correct max_gl*version. - Query the device PCIID via libdrm_nouveau/nouveau_getparam. Signed-off-by: Emil Velikov <[email protected]>
* dri/common: Move __DRI2_RENDERER_PREFFERED_PROFILE handling to ↵Emil Velikov2014-08-153-7/+4
| | | | | | | | | | | | driQueryRendererIntegerCommon Essentially all drivers would like to use to opengl core profile if available, so avoid duplication by moving the code to a common fallback within driQueryRendererIntegerCommon. If a driver uses different approach they can handle it separately. Signed-off-by: Emil Velikov <[email protected]>
* glx/drisw: add support for DRI2rendererQueryExtensionEmil Velikov2014-08-153-2/+58
| | | | | | | | | | The extension is used by GLX_MESA_query_renderer, which can be provided for by hardware and software drivers. v2: Use designated initializers. v3: Move drisw_query_renderer_*() to dri2_query_renderer.c Signed-off-by: Emil Velikov <[email protected]>
* glx/dri2: use mapping table for dri2_convert_glx_query_renderer_attribs()Emil Velikov2014-08-151-26/+28
| | | | Signed-off-by: Emil Velikov <[email protected]>
* glx/drisw: Move private structure declarations to a header fileEmil Velikov2014-08-152-40/+65
| | | | | | v2: Reff the correct file wrt copyright, spotted by Chia-I Signed-off-by: Emil Velikov <[email protected]>
* mesa: check if GL_ARB_copy_image is enabled in _mesa_CopyImageSubData()Brian Paul2014-08-151-1/+7
| | | | | | | | | | Generate a GL error and return rather than crashing on a null ctx->Driver.CopyImageSubData pointer (gallium). This allows apitraces with glCopyImageSubData() calls to continue rather than crash. Plus, fix a comment typo. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp_clear: Use memcpy instead of assignment to copy clear valueNeil Roberts2014-08-151-7/+2
| | | | | | | | | | | | | | Similar to the problem described in 2c50212b14da27de4e3, if we copy the clear value through a regular assignment via a floating point value, then if an integer clear value is being used that happens to contain a signalling NaN value then it would get converted to a quiet NaN when stored via the x87 floating-point registers. This would corrupt the integer value. Instead we should use a memcpy to ensure the exact bit representation is preserved. This bug can be triggered on 32-bit builds with optimisations by using an integer clear color with a value like 0x7f817f81. Reviewed-by: Matt Turner <[email protected]>
* r600g: Implement ARB_derivative_controlGlenn Kennard2014-08-154-12/+14
| | | | | | | | | Requires Evergreen/Cayman marek: update release notes Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* docs: Update relnotes for ARB_gpu_shader5Chris Forbes2014-08-151-1/+1
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* docs: Mark off ARB_gpu_shader5 for i965Chris Forbes2014-08-151-9/+9
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Enable ARB_gpu_shader5 on Gen7Chris Forbes2014-08-151-0/+3
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Add support for nonconst sampler indexing in FS visitorChris Forbes2014-08-152-9/+55
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for non-const sampler indices in generatorChris Forbes2014-08-151-1/+51
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Refactor generate_tex in prep for nonconst sampler indexingChris Forbes2014-08-151-22/+25
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use brw_adjust_sampler_state_pointer in fs generator tooChris Forbes2014-08-151-16/+1
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Add support for nonconst sampler indexing in VS visitorChris Forbes2014-08-152-6/+50
| | | | | | | | V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Add support for non-const sampler indices in generatorChris Forbes2014-08-151-1/+51
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Generalize sampler state pointer mangling for non-constChris Forbes2014-08-151-1/+13
| | | | | | | | | | For now, assume that the addressed sampler can be in any of the 16-sampler banks. If we preserved range information this far, we could avoid emitting these instructions if the sampler were known to be contained within one bank. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Refactor generate_tex in prep for non-const samplersChris Forbes2014-08-151-22/+25
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Extract helper function for surface state pointer adjustmentChris Forbes2014-08-153-16/+41
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* docs: Mark off ARB_gpu_shader5 UBO array indexing for i965Chris Forbes2014-08-151-1/+1
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965/vec4: Add visitor support for nonconst ubo block indexingChris Forbes2014-08-151-3/+26
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965/vec4: Generate indirect sends for nonconstant UBO array accessChris Forbes2014-08-151-15/+62
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965/fs: Add visitor support for nonconstant UBO indicesChris Forbes2014-08-151-3/+27
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965/fs: Generate indirect sends for nonconstant UBO array accessesChris Forbes2014-08-151-39/+135
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965: Adjust set_message_descriptor to handle non-sendsChris Forbes2014-08-151-1/+13
| | | | | | | | | | We're about to be using this infrastructure to build descriptors in src1 of non-send instructions, when preparing to do an indirect send. Don't accidentally clobber the conditionalmod field of those instructions with SFID bits, which aren't part of the descriptor. Signed-off-by: Chris Forbes <[email protected]>
* i965: Add low-level support for indirect sendsChris Forbes2014-08-152-0/+20
| | | | | | | This provides a reasonable place to enforce the hardware restriction that indirect descriptors must be in a0.0 Signed-off-by: Chris Forbes <[email protected]>
* i965/fs: Add pass to rename registers to break live ranges.Kenneth Graunke2014-08-142-0/+68
| | | | | | | | | | | | | | | | | | | The pass breaks live ranges of virtual registers by allocating new registers when it sees an assignment to a virtual GRF it's already seen written. total instructions in shared programs: 4337879 -> 4335014 (-0.07%) instructions in affected programs: 343865 -> 341000 (-0.83%) GAINED: 46 LOST: 1 [mattst88]: Make pass not break in presence of control flow. invalidate_live_intervals() only if progress. Fix up delta_x/delta_y. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965: Fix INTDIV math assertions on Broadwell.Kenneth Graunke2014-08-141-1/+1
| | | | | | | | | | | | | | | | | Commit c66d928f2c9fa59e162c391fbdd37df969959718 ("i965: Enable INTDIV in SIMD16 mode.") began using generate_math_gen6 to break SIMD16 INTDIV into two SIMD8 operations. generate_math_gen6 takes two registers - for unary operations, we pass ARF null for the second operand. Prior to Broadwell, real operands were always GRF. But now they can be IMM as well. So, check for != ARF instead of == GRF. +12 piglits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* Revert "i965/vec4: Use MOV, not OR, to set URB write channel mask bits."Kenneth Graunke2014-08-141-2/+4
| | | | | | | | | | | | | | | This reverts commit af13cf609f4257768ad8b80be8cec7f2e6ca8c81, which appears to cause huge performance problems on Ivybridge. I'd missed that the FFTID bits are in the low byte. The documentation doesn't indicate that the URB write message header actually wants FFTID - it just labels those bits as "Reserved." But it appears necessary. This does slightly more than revert the original change: originally, Broadwell had separate code generation, which used MOV, and this patch only changed it for Gen4-7. Now that both are unified, reverting this also makes Broadwell use OR. Which should be fine. Signed-off-by: Kenneth Graunke <[email protected]>
* docs: Mark off ARB_derivative_control for i965.Chris Forbes2014-08-152-2/+2
| | | | | | | Also update 10.3 relnotes to match. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Enable ARB_derivative_control on Gen7+.Chris Forbes2014-08-151-0/+1
| | | | | | | | | | The extension says GL 4.0 is required. We'll meet the spirit of that restriction by enabling on just those generations which will soon support GL 4.0 (Gen7+), although it's technically supportable on all generations. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Support fine/coarse derivative opcodesChris Forbes2014-08-155-10/+44
| | | | | | | | The quality level (fine/coarse/dont-care) is plumbed through to the generator as a constant in src1. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Assert that fine/coarse derivative ops don't appearChris Forbes2014-08-151-0/+4
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Mark program as using dFdy if coarse/fine variant is usedChris Forbes2014-08-151-1/+3
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nv50,nvc0: add support for fine derivativesIlia Mirkin2014-08-145-3/+8
| | | | | | | The quadop-based method we currently use on all chipsets already provides the fine version of the derivatives. Signed-off-by: Ilia Mirkin <[email protected]>
* mesa/st: add support for emitting fine derivative opcodesIlia Mirkin2014-08-142-2/+10
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add opcodes/cap for fine derivative supportIlia Mirkin2014-08-1419-5/+34
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) Reviewed-by: Roland Scheidegger <[email protected]> (v1) v2: Reuse opcode gaps as suggested by Marek
* mesa/program: add new derivative unops to the unexpected listIlia Mirkin2014-08-141-0/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* glsl: add ARB_derivative control supportIlia Mirkin2014-08-148-0/+74
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: add ARB_derivative_control extension bitIlia Mirkin2014-08-142-0/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: add ARB_texture_barrier supportIlia Mirkin2014-08-146-1/+21
| | | | | | | | | This extension is identical to NV_texture_barrier. Alias glTextureBarrier to the existing glTextureBarrierNV and use the existing NV_texture_barrier extension bit. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* docs: document radeonsi BPTC support, sort extensions in 10.3 release notesMarek Olšák2014-08-152-6/+6
|
* r600g: Implement BPTC texture supportGlenn Kennard2014-08-153-2/+26
| | | | | | | Requires Evergreen/Cayman Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* i965: Rename intelValidateState to intel_update_stateKristian Høgsberg2014-08-142-9/+7
| | | | | | | | This matches the name of the dd hook. Also convert a couple of nearby dd implementations to lowercase + underscore as is now the standard. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Assign PS kernel start pointers when we decide which kernels to useKristian Høgsberg2014-08-143-23/+28
| | | | | | | | | | | Right now we decide which kernels to use and the GRF start offsets in one place and emit the kernel pointers later. The logic of how to map 8, 16 and 32 kernels to kernel start pointers follows the same logic as which GRF start offsets to use, so lets figure out these two things in one place. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* radeonsi: implement BPTC texture supportGrigori Goronzy2014-08-141-0/+20
| | | | | | | | Passes all piglit tests. v2: rebased Signed-off-by: Marek Olšák <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 01:02:53 +0000