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* st/va: Check NULL pointerGurkirpal Singh2016-06-271-0/+4
| | | | | | | | | | Call to handle_table_get in vlVaDestroySurfaces can return NULL on failure. CID: 1243522 Signed-off-by: Gurkirpal Singh <[email protected]> Reviewed-by: Julien Isorce <[email protected]>
* nir: Fix copy_prop_src when src is an indirect access on a reg.Eric Anholt2016-06-261-1/+1
| | | | | | | | | | | | The intent was to continue down the indirect chain, not to call ourselves with unchanged input arguments. Found by code inspection, and comparison to copy_prop_alu_src(). We haven't hit this because callers of NIR's copy prop are doing so in SSA, before indirect variable dereferences have been lowered to registers. Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* gm107/ir: make use of MOV32I for all immediatesSamuel Pitoiset2016-06-271-2/+1
| | | | | | | | | MOV only allows to emit 19-bits immediates. This is similar to the previous fix I did for IMUL. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* i965: Use miptree to decide format on multi-plane images for gen < 7Jordan Justen2016-06-261-1/+2
| | | | | | | | | | | This wasn't handled correctly for multi-plane images on gen < 7 in 727a9b24933d384f5440ed4318fb720ed11d6dd1. Reported-by: Mark Janes <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96674 Signed-off-by: Jordan Justen <[email protected]> Cc: "12.0" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nvc0: update "derived" state function namesIlia Mirkin2016-06-261-8/+8
| | | | | | | derived_1/2/etc aren't too informative. Instead name them based on the state they're derived from. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: provide support for unscaled poly offset unitsIlia Mirkin2016-06-263-3/+26
| | | | | | | | On at least Kepler hardware, the units differ based on RT format. Emit a properly scaled value for Z16 depth buffers vs other formats, to help out st/nine. Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: make use of IMUL32I for all immediatesSamuel Pitoiset2016-06-261-1/+1
| | | | | | | | | | IMUL only allows to emit 19-bits immediates. This is similar to d30768025a2283d4cc57930b784798bf278969da which fixed the same thing for the GK110 emitter. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* radeonsi: make si_is_format_supported staticMarek Olšák2016-06-253-11/+6
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: boolean -> bool, TRUE -> true, FALSE -> falseMarek Olšák2016-06-254-15/+15
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: boolean -> bool, TRUE -> true, FALSE -> falseMarek Olšák2016-06-259-75/+75
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon/winsyses: boolean -> bool, TRUE -> true, FALSE -> falseMarek Olšák2016-06-259-132/+134
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use r600_resource_referenceMarek Olšák2016-06-2512-40/+32
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nir: Add a NIR_VALIDATE environment variableJason Ekstrand2016-06-251-0/+6
| | | | | | | | | | | It defaults to true so default behavior doesn't change but it allows you to do NIR_VALIDATE=false if you don't want validation. Disabling validation can substantially speed up shader compiles so you frequently want to turn it off if compiler invariants aren't in question. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* st/nine: Use offset_units_unscaledAxel Davy2016-06-255-11/+13
| | | | | | | | | | | | offset_units_unscaled enables proper support for depth bias for gallium nine. Use it if available. Solves issues with some games using depth bias. For example: https://github.com/iXit/Mesa-3D/issues/220 Signed-off-by: Axel Davy <[email protected]>
* r600g: Implement POLYGON_OFFSET_UNITS_UNSCALEDAxel Davy2016-06-255-36/+46
| | | | | | | | | | | | | | | | Empirical tests show that the polygon offset behaviour is entirely determined by the content of the PA_SU_POLY_OFFSET states, and not by the depth buffer format bound. PA_SU_POLY_OFFSET seems to directly set the parameters of the polygon offset formula, and setting 0 for PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled behaviour. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Implement POLYGON_OFFSET_UNITS_UNSCALEDAxel Davy2016-06-252-15/+19
| | | | | | | | | | | | | | | | Empirical tests show that the polygon offset behaviour is entirely determined by the content of the PA_SU_POLY_OFFSET states, and not by the depth buffer format bound. PA_SU_POLY_OFFSET seems to directly set the parameters of the polygon offset formula, and setting 0 for PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled behaviour. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon: Remove useless pa_su_poly_offset_db_fmt_cntlAxel Davy2016-06-251-1/+0
| | | | | | | | pa_su_poly_offset_db_fmt_cntl usages were removed in previous patches. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for evergreenAxel Davy2016-06-251-25/+13
| | | | | | | | | | | Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states. This will be useful to implement PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. v2: Increase the num_dw field for the poly offset atom Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for r600Axel Davy2016-06-251-24/+13
| | | | | | | | | | | Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states. This will be useful to implement PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. v2: Increase the num_dw field for the poly offset atom Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset statesAxel Davy2016-06-251-23/+8
| | | | | | | | | Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with rasterizer poly_offset states. This will be useful to implement PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Add a cap for offset_units_unscaledAxel Davy2016-06-2519-0/+31
| | | | | | | | | | | | | | D3D9 has a different behaviour for depth bias. For OGL/D3D1X, the depth bias unit is the minimal resolvable value for the depth buffer, which depends on the format (and has different behaviour for float depth buffers). For D3D9, the depth bias unit is 1.0f. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Skip update_texture_surface when the plane doesn't existJordan Justen2016-06-243-29/+26
| | | | | | | | | Reported-by: Grazvydas Ignotas <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96607 Signed-off-by: Jordan Justen <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: "12.0" <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Validate a few SEND-from-GRF requirements.Kenneth Graunke2016-06-241-0/+18
| | | | | | | | | We recently had a mistake where we emitted SEND instructions with EOT set, but from g107 rather than g112-g127. Adding validation code should prevent these sorts of problems from slipping back in. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Delete send-from-GRF only opcodes from implied_mrf_writes().Kenneth Graunke2016-06-241-19/+0
| | | | | | | | | These only exist post-Sandybridge, and always use send-from-GRF. So inst->base_mrf will be -1, and we will have already returned 0. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Drop unnecessary inst->base_mrf = -1 assignments.Kenneth Graunke2016-06-242-16/+0
| | | | | | | | These are now unnecessary, as base_mrf is -1 by default. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Set fs_inst::base_mrf = -1 by default.Kenneth Graunke2016-06-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | On MRF platforms, we need to set base_mrf to the first MRF value we'd like to use for the message. On send-from-GRF platforms, we set it to -1 to indicate that the operation doesn't use MRFs. As MRF platforms are becoming increasingly a thing of the past, we've forgotten to bother with this. It makes more sense to set it to -1 by default, so we don't have to think about it for new code. I searched the code for every instance of 'mlen =' in brw_fs*cpp, and it appears that all MRF-based messages correctly program a base_mrf. Forgetting to set base_mrf = -1 can confuse the register allocator, causing it to think we have a large fake-MRF region. This ends up moving the send-with-EOT registers earlier, sometimes even out of the g112-g127 range, which is illegal. For example, this fixes illegal sends in Piglit's arb_gpu_shader_fp64-layout-std430-fp64-shader, which had SSBO messages with mlen > 0 but base_mrf == 0. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Drop unused return value from intel_finalize_mipmap_tree().Kenneth Graunke2016-06-242-7/+5
| | | | | | | | | | | | The old return type of GLuint was wonky - it should have been bool. But nothing actually uses the return value anyway, so we can just drop that and make it a void function. In theory, it might make sense to ask whether the texture validated successfully, but just checking intel_obj->mt != NULL works for that. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Move contents of brw_tex.c into intel_tex_validate.c.Kenneth Graunke2016-06-244-58/+20
| | | | | | | | | | | brw_tex.c is a tiny file containing a single function. It's closely tied to the validation logic in intel_tex_validate.c, so it makes sense to put both in the same file. While we're at it, update the function to our modern style. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* radeonsi: fix fractional odd tessellation spacing for PolarisMarek Olšák2016-06-244-1/+23
| | | | | | | ported from Vulkan (and no source explains why this is needed) Cc: 12.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set some VGT context registers on SI-CIMarek Olšák2016-06-241-0/+3
| | | | | | the kernel sets them, but other UMDs can change them Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: optimize rendering to linear color buffersMarek Olšák2016-06-242-1/+12
| | | | | | loosely ported from Vulkan Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set almost optimal settings in SC_MODE_CNTL_1Marek Olšák2016-06-241-1/+10
| | | | | | ported from Vulkan Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: let drivers specify SC_MODE_CNTL_1 fieldsMarek Olšák2016-06-244-10/+18
| | | | | | radeonsi will set more fields Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: disable complicated point clipping against user clip planesMarek Olšák2016-06-243-3/+0
| | | | | | Nothing in the GL spec says that we should expand points to triangles. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix a compute shader hang with big threadgroups on SI & CIMarek Olšák2016-06-241-0/+18
| | | | | | | ported from Vulkan Cc: 12.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nvc0: when mapping directly, provide accurate xfer info + startIlia Mirkin2016-06-241-5/+12
| | | | | | | | | | We were ignoring the incoming box parameters, and were providing totally bogus stride/layer stride, and other bits, for when a non-full-surface map was requested. Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Samuel Pitoiset <[email protected]> Cc: <[email protected]>
* st/mesa: don't assume that the whole surface gets mappedIlia Mirkin2016-06-241-7/+6
| | | | | | | | | | Under some circumstances, the driver may choose to return a temporary surface instead of a pointer to the original. Make sure to pass the actual view volume to be mapped to the transfer function rather than adjusting the map pointer after-the-fact. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: drop the DRAW_PREAMBLE packet on PolarisNicolai Hähnle2016-06-242-1/+28
| | | | | | | | It will be removed from the firmware for the Polaris. Cc: 12.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on PolarisNicolai Hähnle2016-06-241-10/+36
| | | | | | | | The non-MULTI variants will be removed in Polaris firmware. Cc: 12.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: handle negative _ColorDrawBufferIndexes values correctlyFrancesco Ansanelli2016-06-241-1/+1
| | | | Signed-off-by: Marek Olšák <[email protected]>
* winsys/radeon: add guard pages when R600_DEBUG=check_vm is enabledNicolai Hähnle2016-06-243-2/+7
| | | | | | This should help flush out GPU VM faults. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add guard pages when R600_DEBUG=check_vm is enabledNicolai Hähnle2016-06-243-2/+8
| | | | | | This should help flush out GPU VM faults. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: report a failure to parse dmesg instead of assertingNicolai Hähnle2016-06-241-1/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon: check VM faults from DMA flushNicolai Hähnle2016-06-245-6/+68
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move gfx fence wait out of si_check_vm_faultsNicolai Hähnle2016-06-242-6/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: extract IB and bo list saving into separate functionsNicolai Hähnle2016-06-246-54/+88
| | | | Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: fix readpixels regression with MESA_pack_invertNicolai Hähnle2016-06-241-1/+1
| | | | | | | | Fixes an error introduced in commit 3948cd37973696dc319170877382676809659465. Reported-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: set LLVM denormal flagsMarek Olšák2016-06-241-2/+5
| | | | | | | | | - make sure FP32 denormals will stay disabled in LLVM in the future (the current default is disabled) - tell LLVM that FP64 denormals are enabled Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit 1/sqrt for RSQMarek Olšák2016-06-241-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need the clamped version and we don't have to use any intrinsic. Stats on Tonga: 15382 shaders in 9128 tests Totals: SGPRS: 1230560 -> 1230560 (0.00 %) VGPRS: 469577 -> 462504 (-1.51 %) Code Size: 22089908 -> 21730052 (-1.63 %) bytes LDS: 598 -> 598 (0.00 %) blocks Scratch: 283648 -> 281600 (-0.72 %) bytes per wave Max Waves: 125664 -> 126969 (1.04 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 547280 -> 547280 (0.00 %) VGPRS: 269132 -> 262059 (-2.63 %) Code Size: 15709604 -> 15349748 (-2.29 %) bytes LDS: 198 -> 198 (0.00 %) blocks Scratch: 74752 -> 72704 (-2.74 %) bytes per wave Max Waves: 47840 -> 49145 (2.73 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g: Enable FMA on chips that support itJan Vesely2016-06-242-5/+7
| | | | | | | | | | v2: Merge with PIPE_SHADER_CAP_DOUBLES Add CHIP_HEMLOCK v3: only set the instruction on EG and CM Signed-off-by: Jan Vesely <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
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