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* nir: Add lower_rotate flag and set to true in all driversSagar Ghuge2019-07-019-0/+11
* intel/compiler: Emit ROR and ROL instructionSagar Ghuge2019-07-012-0/+9
* nir: Add optimization to use ROR/ROL instructionsSagar Ghuge2019-07-012-0/+15
* nir: Add urol and uror opcodesSagar Ghuge2019-07-011-0/+11
* intel/compiler: Enable the emission of ROR/ROL instructionsSagar Ghuge2019-07-016-2/+26
* panfrost: Implement instanced renderingAlyssa Rosenzweig2019-07-019-60/+568
* panfrost/decode: Compute padded_num_vertices for MODULOAlyssa Rosenzweig2019-07-011-2/+12
* panfrost/midgard: Emit type appropriate ld_varyAlyssa Rosenzweig2019-07-011-2/+19
* panfrost/midgard: Add unsigned ld/st opsAlyssa Rosenzweig2019-07-013-1/+11
* panfrost/midgard: Use the appropriate ld_attr typeAlyssa Rosenzweig2019-07-011-0/+20
* panfrost: Implement dispatch helpersAlyssa Rosenzweig2019-07-014-13/+165
* panfrost: Remove ancient commentAlyssa Rosenzweig2019-07-011-3/+0
* panfrost: Extend software tiling to larger bppAlyssa Rosenzweig2019-07-011-9/+49
* panfrost: Rewrite u-interleaving codeAlyssa Rosenzweig2019-07-011-101/+189
* freedreno: update generated registersRob Clark2019-07-017-16/+23
* radv: rework how the number of VGPRs is computedSamuel Pitoiset2019-07-013-26/+31
* radv: gather if a vertex shaders needs the instance IDSamuel Pitoiset2019-07-011-4/+14
* radv: fix decompressing DCC levels with computeSamuel Pitoiset2019-07-011-1/+7
* radv: the number of VGPR_COMP_CNT for GS is expected to be 0 on GFX8Samuel Pitoiset2019-07-011-1/+1
* radv: reduce number of VGPRs for TESS_EVAL if primitive ID is not usedSamuel Pitoiset2019-07-011-3/+10
* radv: make sure to mark the image as compressed when clearing DCC levelsSamuel Pitoiset2019-07-013-27/+8
* targets/opencl: Add clangASTMatchers library as dependencyMichel Dänzer2019-07-011-0/+1
* glsl/nir: Lower buffers using Binding instead of NamesCaio Marcelo de Oliveira Filho2019-06-301-5/+28
* glspirv: Enable the new deref-base UBO/SSBO path on gl_spirvAlejandro Piñeiro2019-06-301-2/+10
* i965: call to gl_nir_link_uniform_blocksAlejandro Piñeiro2019-06-301-0/+4
* i965: use GLboolean for all brw_link_shader returnsAlejandro Piñeiro2019-06-301-3/+3
* nir/linker: update already processed uniforms search for UBOs/SSBOsAlejandro Piñeiro2019-06-301-10/+71
* nir/linker: fill up uniform_storage with explicit dataAlejandro Piñeiro2019-06-301-5/+47
* nir/linker: use only the array element type for array of ssbo/uboAlejandro Piñeiro2019-06-301-2/+42
* nir/linker: fill is_shader_storage for uniformsAlejandro Piñeiro2019-06-301-1/+2
* nir/linker: add gl_nir_link_uniform_blocks.cAlejandro Piñeiro2019-06-304-0/+648
* nir_types: add glsl_type_is_leaf helperAlejandro Piñeiro2019-06-302-0/+15
* glsl/nir: add glsl_types::explicit_size plus nir C wrapperAlejandro Piñeiro2019-06-304-0/+89
* glsl_types: add type::bit_size and glsl_base_type_bit_size helpersAlejandro Piñeiro2019-06-301-8/+52
* nir: add is_in_ubo/ssbo/block helpersAlejandro Piñeiro2019-06-301-0/+20
* spirv/nir: fill up nir variable info for ubos and ssboAlejandro Piñeiro2019-06-301-1/+3
* spirv/nir: create nir variable for UBO/SSBOAlejandro Piñeiro2019-06-301-2/+13
* vl: Use CS composite shader only if TEX_LZ and DIV are supportedGert Wollny2019-06-302-8/+11
* gallium: Add CAP for opcode DIVGert Wollny2019-06-3010-0/+11
* vl: replace DIV-ADD with MAD using inverse sizeGert Wollny2019-06-301-4/+5
* etnaviv: blt: blit with the original format when possibleJonathan Marek2019-06-291-7/+11
* etnaviv: clear all bits for 24bpp depth without stencilJonathan Marek2019-06-291-1/+1
* mesa: use binary search for MESA_EXTENSION_OVERRIDEEric Engestrom2019-06-301-6/+16
* gitlab-ci: test meson installationEric Engestrom2019-06-291-0/+1
* anv: fix indentationEric Engestrom2019-06-291-15/+14
* anv: fix typoEric Engestrom2019-06-291-1/+1
* anv: replace hard-coded platform list with vk.xml parseEric Engestrom2019-06-291-5/+11
* android: fix typo LOCAL_EXPORT_C_INCLUDESChih-Wei Huang2019-06-292-2/+2
* android: virgl: fix generated virgl_driinfo.h building rulesMauro Rossi2019-06-291-2/+8
* intel/compiler: don't use byte operands for src1 on ICLLionel Landwerlin2019-06-294-20/+192
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