| Commit message (Collapse) | Author | Age | Files | Lines |
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anv_image::needs_sampler_surface_state was a redundant member,
identical to (usage & VK_IMAGE_USAGE_SAMPLED_BIT). Likewise for the
other needs_* members.
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Let's call it what it is, not what it is not. Rename it to
'sampler_surface_state'.
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We weren't pulling the actual binding location information out of the set
layout. The new code mirrors the descriptor write code.
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When generating a sub-determinate matrix, a 3-element swizzle array was
indexed with clever inline boolean logic. Unfortunately, when i and j
are both 3, the index overruns the array, smashing the next variable on
the stack.
For 64 bit builds, the alignment of the 3-element unsigned array leaves
32 bits of spacing before the next local variable, hiding this bug. On
i386, a subcolumn pointer was smashed then dereferenced.
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anv_descriptor_set_destroy uses the descriptor sets's set_layout member
to iterate the set's buffer views. However, the set_layout reference
may have previously been freed.
On 64 bit builds, this bug generated valgrind errors but did not affect
CTS test results. On 32 bit builds, it reliably produces assertions and
memory corruption.
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Otherwise we may get a lib vs lib64 mismatch.
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This is kind-of silly. We *really* need to do a better job of making sure
all objects have all their default values set. We probably also want to,
eventually, put everything into the BO (to save memory) and, more
specifically, make the GPU write the "ready" flag. That way GetFenceStatus
won't ever have to call into the kernel.
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bit-shifts on 32 bit unsigned longs overflow in several places. The
intention was for 64 bit integers to be used.
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After a long discussion with Eric Anholt and Owen Taylor, I learned that
X11 is basically always sRGB as that's what the scanout hardware does and X
doesn't modify anything. Therefore, we should just always expose sRGB
formats.
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anv_descriptor contained a union with one member.
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The GPU does most of this for us as long as we set up tight bounds for
the buffers, which we do. Additionally, we range check dynamically
buffers in the shader. With that it's safe to turn on robustBufferAccess.
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We don't actually support that format yet because ISL doesn't have an enum
for it. We need to beef up the formats table to allow for tiled-only
formats.
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Signed-off-by: Jordan Justen <[email protected]>
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Signed-off-by: Jordan Justen <[email protected]>
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Signed-off-by: Jordan Justen <[email protected]>
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Signed-off-by: Jordan Justen <[email protected]>
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Signed-off-by: Jordan Justen <[email protected]>
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e8f51fe4 for gen7
Signed-off-by: Jordan Justen <[email protected]>
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292031a for gen7
Signed-off-by: Jordan Justen <[email protected]>
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Signed-off-by: Jordan Justen <[email protected]>
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Signed-off-by: Jordan Justen <[email protected]>
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Adds initial compute_pipeline_create implementation for gen7.
Signed-off-by: Jordan Justen <[email protected]>
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Vulkan WSI Wayland fixes
Two small fixes to make mailbox mode actually work again.
See merge request !4
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We were diligently setting Wayland buffers as non-busy, but nowhere in
the code did we set them to busy when submitted to the server. This
meant that acquire_next_image would only ever find the same buffer in
a loop, over and over.
Signed-off-by: Daniel Stone <[email protected]>
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In acquire_next_image, we are waiting for a wl_buffer::release to arrive
and release one of the buffers in our swapchain. Most compositors don't
explicitly flush release events, so we may need to perform a roundtrip
instead, to ensure the event arrives.
Signed-off-by: Daniel Stone <[email protected]>
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They're just images and we have no intention of stompping alpha channels
(at least not yet), so there's no reason why you can't sample.
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This adds support for the DX compression formats. Given that ETC and EAC
are working fine, these should be ok too.
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The bottom-end check was wrong so it was only working on <= 1.0.0. Oops.
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There's an intermittent flushing problem with VkEvent that we need to
root cause. For now, using the snooping feature keeps the memory pools
up to date with GPU writes and fixes the problem.
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We can't use the more fine-grained load and store fence commands (lfence
and mfence), since clflush is only guaranteed to be ordered with respect
to mfence.
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The state for line width changes on Cherryview to use the GEN9 bits (for extra
precision).
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For upcoming patch to address difference in Cherryview.
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