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* i965: Move VS pull constant upload to emit() time.Eric Anholt2011-10-291-2/+2
| | | | | | | Only needed by the emit() for VS surfaces. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Fold prepare() and emit() of VS surface state setup together.Eric Anholt2011-10-291-37/+25
| | | | | | | | This rearranges the code a bit, and makes the upload of the binding table take only as many surfaces as there are in use. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Move WM pull constant setup to emit() time.Eric Anholt2011-10-291-2/+2
| | | | | | | It's needed by the WM surface state setup, which is now emit(). Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965/gen7: Fold WM surface state prepare()/emit() together.Eric Anholt2011-10-291-38/+18
| | | | | | | | | | | These produce BRW_NEW_SURFACES (used by binding table emit()) and BRW_NEW_NR_WM_SURFACES (used by WM unit emit()). Fixes a bug where with no texturing and no color buffer, we wouldn't consider the null renderbuffer in nr_surfaces. This was harmless because nr_surfaces is only used for the prefetch info in the unit state. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965/gen4: Fold WM surface state prepare()/emit() together.Eric Anholt2011-10-291-36/+18
| | | | | | | | | | | These produce BRW_NEW_SURFACES (used by binding table emit()) and BRW_NEW_NR_WM_SURFACES (used by WM unit emit()). Fixes a bug where with no texturing and no color buffer, we wouldn't consider the null renderbuffer in nr_surfaces. This was harmless because nr_surfaces is only used for the prefetch info in the unit state. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Move sampler state to emit() time.Eric Anholt2011-10-292-4/+4
| | | | | | | This is consumed by the WM unit, which is already at emit(). Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965/gen4: Move unit state setup to emit() time.Eric Anholt2011-10-296-10/+11
| | | | | | | It is only needed in time for brw_psp_urb_cbs(), which is also an emit(). Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965/gen7: Fold prepare() and emit() of SF CLIP/VP state together.Eric Anholt2011-10-291-9/+4
| | | | | | | The prepare() only made state for its emit(), not anybody else. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965/gen4: Move CC VP to emit() time, since it's only needed by CC's emit().Eric Anholt2011-10-291-2/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Move push constants setup to emit() time.Eric Anholt2011-10-292-6/+6
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965/gen6: Move setup of CC state batches to emit time.Eric Anholt2011-10-292-6/+6
| | | | | | | | | | This is part of a series trying to eliminate the separate prepare() hook in state upload. The prepare() hook existed to support the check_aperture in between calculating state updates and setting up the batch, but there should be no reason for that any more. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Check Fallback again after upload.Eric Anholt2011-10-291-1/+6
| | | | | | | | As we move state to emit() time from prepare() time, a couple of the places that flag fallbacks will move here. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Remove the validated BO list, now that it's unused.Eric Anholt2011-10-2912-109/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Use the batch save/reset code to avoid needing the BO validate step.Eric Anholt2011-10-291-33/+27
| | | | | | | | | | | | | | | | | | We were doing the BO validate step in prepare() (brw_validate_state()) hooks of atoms so that we could check_aperture before emitting the relocation trees during brw_upload_state() that would actually make the batchbuffer reference too much memory to be executed. Now that all relocations occur in the batchbuffer, we can instead check_aperture after emitting our state into the batchbuffer, and easily roll back, flush, and retry if we happened to go over the limits. This will let us remove the whole prepare() vs emit() split in our state atoms, which is a source of tricky dependencies and duplicated code. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Return error value from intel_batchbuffer_flush().Eric Anholt2011-10-292-6/+12
| | | | | | | This will let the caller do something sensible on error, if it cares. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Add a note about an unsafe-looking state check.Eric Anholt2011-10-291-0/+5
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Add an interface for saving/restoring the batchbuffer state.Eric Anholt2011-10-294-1/+29
| | | | | | | | | | This will be used to avoid the prepare() step in the i965 driver's state setup. Instead, we can just speculatively emit the primitive into the batchbuffer, then check if the batch is too big, rollback and flush, and replay the primitive. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i915: Move the always_flush_cache code to triangle emit.Eric Anholt2011-10-292-4/+8
| | | | | | | | | | | This could have broken always_flush_cache on i965, since reserved_space doesn't reflect the size of the workaround flushes, and we might run out of space. This should make always_flush_cache more useful on pre-i965, anyway (since the point is to flush around each draw call, even within a batchbuffer). Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* glsl: Fix compilation of glsl_lexer.ll with MSVC.Morgan Armand2011-10-291-0/+4
| | | | strtoull is not supported on msvc (as there is no C99 support).
* r600g: Replace needless flush in texture upload.Mathias Fröhlich2011-10-291-1/+1
| | | | | | | Replace pipe->flush() with pipe->texture_barrier() in the texture upload path for the staging texture. This should be enough to get data out of the gpu caches ready to be read for texture fetch.
* r600g: remove one pointless flushMarek Olšák2011-10-293-25/+4
| | | | | | | | It's not useful for anything. The rest of the patch is just a cleanup resulting from some of the variables being no longer used. There are no piglit regressions.
* radeon/r200: forgot one somehowDave Airlie2011-10-291-1/+2
| | | | drops last usage.
* radeon/r200: drop remains of non-libdrm_radeon buildDave Airlie2011-10-2914-351/+4
| | | | | | These wrappers and associated symlinks were from the non-libdrm_radeon build. Signed-off-by: Dave Airlie <[email protected]>
* mesa/st: get interpolation mode from the fragment shader.Dave Airlie2011-10-291-1/+15
| | | | | | | | | With the recent changes to interpolation stuff, we can now get the value direct from the program instead of just being fail. fixes some of the glsl-1.30 interpolation tests with softpipe Signed-off-by: Dave Airlie <[email protected]>
* glx: Don't enable INTEL_swap_event unconditionallyAdam Jackson2011-10-281-1/+1
| | | | | | | | DRI2 supports this now - and already enables it explicitly - but drisw does not and should not. Otherwise toolkits like clutter will only ever SwapBuffers once and wait forever for an event that's not coming. Signed-off-by: Adam Jackson <[email protected]>
* implement WGL_ARB_create_contextMorgan Armand2011-10-285-7/+166
| | | | Signed-off-by: José Fonseca <[email protected]>
* r600g: get backend mask after the context is fully set upMarek Olšák2011-10-283-4/+2
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* ir_to_mesa: Let check_resources halt compilationIan Romanick2011-10-281-6/+17
| | | | | | | | | | | | | | | | Previously check_resources could fail, but we'd still try to optimize the shader, do device-specific code generation, etc. In some cases, this could explode (especially in the device-specific code generation). I haven't found that I could trigger this with the current code. When too many samplers were used with the new uniform handling code, I observed several crashes deep down in the driver. NOTE: This is candidate for the 7.11 branch. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41609 Cc: Eric Anholt <[email protected]> Reviewed-and-tested-by: Kenneth Graunke <[email protected]>
* i965: Use glsl_type::column_type instead of open-coding itIan Romanick2011-10-281-3/+1
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Clean-up spurious error message on bad structure definitionsIan Romanick2011-10-281-6/+24
| | | | | | | | | | | | | | | | | | | Previously a shader like int X; struct X { int i; }; void main() { gl_Position = vec4(0.0); } would generate two error message: 0:2(19): error: struct `X' previously defined 0:2(20): error: incomplete declaration The first one is the real error, and the second is spurious. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Generate an error for array-of-array declarationsIan Romanick2011-10-281-2/+14
| | | | | | | | | | | | Other parts of the code already caught things like 'float x[4][2]'. However, nothing caught 'float [4] x[2]'. Fixes piglit test array-multidimensional-new-syntax.vert. NOTE: This is candidate for the 7.11 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r300c/compiler: remove the compiler tooMarek Olšák2011-10-2861-17084/+0
| | | | Gallium has a fork of this.
* i965/fs: Use the actual hardware g0 register for texel offset setup.Kenneth Graunke2011-10-281-1/+1
| | | | | | | | | | | | | | | | | | The idea here is to set up the message header with the Sampler State pointer which the hardware provides as part of the PS Thread Payload in register g0. Unfortunately, the existing code fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)) actually references "virtual GRF 0" rather than the hardware g0. This is just some arbitrary GRF temporary which will get register allocated. So, we ended up setting up the header with garbage. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* u_format: Fix -NaN handling for packing of 10F_11F_11F_REV to match GL specs.Eric Anholt2011-10-281-11/+31
| | | | | | | Fixes the remainder of piglit GL_EXT_packed_float/pack.c Reviewed-by: Marek Ol ák <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* u_format: Fix clamping of overflow in 10F_11F_11F_REV to match GL specs.Eric Anholt2011-10-281-4/+18
| | | | | | | | Fixes the 1000000.0 overflow cases of piglit GL_EXT_packed_float/pack.c Reviewed-by: Marek Ol ák <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Don't do [0, 1] clamping on glGetTexImage() of packed float formats.Eric Anholt2011-10-281-4/+6
| | | | | | | | | | | | | | | | | | | | From the GL_EXT_packed_float spec: For an RGBA color, if <type> is not one of FLOAT, UNSIGNED_INT_5_9_9_9_REV_EXT, or UNSIGNED_INT_10F_11F_11F_REV_EXT, or if the CLAMP_READ_COLOR_ARB is TRUE, or CLAMP_READ_COLOR_ARB is FIXED_ONLY_ARB and the selected color (or texture) buffer is a fixed-point buffer, each component is first clamped to [0,1]. Then the appropriate conversion formula from table 4.7 is applied the component." (but we previously resolved that the CLAMP_READ_COLOR bit is not relevant to glGetTexImage()) This fixes most of the cases in piglit GL_EXT_packed_float/pack. Reviewed-by: Marek Ol ák <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* u_format: Fix bitshifting for unpacking from 10F.Eric Anholt2011-10-281-2/+2
| | | | | | | | | This code was copy and pasted from the 11F unpacking, but not updated for actually being 10 bits instead of 11. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41206 Reviewed-by: Marek Ol ák <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* u_format: Fix bit definition of UF10_MANTISSA_BITS.Eric Anholt2011-10-281-1/+1
| | | | | | | | | This is only used in the code for packing to INF, and resulted in an extra bit set that was set anyway, so it was harmless except for the confusion caused. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Implement GLSL 1.30's literal integer range restrictions.Eric Anholt2011-10-281-8/+45
| | | | | | | | | | | | | | | | From page 22 (28 of PDF) of GLSL 1.30 spec: It is an error to provide a literal integer whose magnitude is too large to store in a variable of matching signed or unsigned type. Unsigned integers have exactly 32 bits of precision. Signed integers use 32 bits, including a sign bit, in two's complement form. Fixes piglit int-literal-too-large-0[123].frag. v2: Take care with INT_MIN, use stroull, and make it a function. Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radeon: Remove the non-libdrm kernel memory manager support.Eric Anholt2011-10-288-464/+2
| | | | We should have never been building this at this point.
* radeon: Insist on libdrm being present to build.Eric Anholt2011-10-285-110/+5
| | | | | | | There's no sense in building a broken driver. Previously, there was the potential of building a DRI1-only driver that would work for DRI1 and fail on DRI2 because the newer libdrm code wasn't present. Now the radeon build system should be matching intel and nouveau.
* configure.ac: Fix equality checks in gallium st setup.Eric Anholt2011-10-281-3/+3
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* dri: Remove driver GenerateMipmap hooks.Eric Anholt2011-10-284-67/+0
| | | | | Mesa sets up _mesa_meta_GenerateMipmap as the default hook, which does this check for fallback and call the fallback itself.
* radeon: Drop some remaining DRI1 vblank support code.Eric Anholt2011-10-283-58/+0
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* intel: remove dead prototype for old DRI1 code.Eric Anholt2011-10-281-5/+0
| | | | Noticed while grepping for radeon code.
* radeon: Simplify cliprects computation now that there's just 1.Eric Anholt2011-10-283-69/+15
| | | | | | This can probably be reduced even further by moving this logic to the scissor state update or just removing the logic entirely, but I don't trust myself in radeon quite that much.
* radeon: Drop the clipping in spans, now that we always have (0,0) -> (w,h).Eric Anholt2011-10-281-54/+38
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* radeon: Drop the legacy BO manager code.Eric Anholt2011-10-287-988/+0
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* radeon: Drop the DRI1 zero-copy TFP code.Eric Anholt2011-10-285-92/+0
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* radeon: Drop the radeon_cs_legacy code now that we rely on kernel mm.Eric Anholt2011-10-286-458/+0
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