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* glsl: Fix off-by-one error in array size check assertionIan Romanick2015-11-181-2/+1
| | | | | | | | | | Apparently, this has been a bug since 2010 (c30f6e5d). Also use ARRAY_SIZE instead of open coding it. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* mesa: Don't expose GL_EXT_shader_integer_mix in GLES 1.xIan Romanick2015-11-181-1/+1
| | | | | | | | | There are no shaders, so it doesn't even make sense to expose the extension. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: Nanley Chery <[email protected]>
* glsl: Silence unused parameter warningsIan Romanick2015-11-181-2/+2
| | | | | | | | | | | | builtin_functions.cpp:5289:52: warning: unused parameter 'num_arguments' [-Wunused-parameter] unsigned num_arguments, ^ builtin_functions.cpp:5290:52: warning: unused parameter 'flags' [-Wunused-parameter] unsigned flags) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: Silence ignored qualifier warningIan Romanick2015-11-181-1/+1
| | | | | | | | | | | | | I think the intention was to mark the "this" parameter as const, but const goes on the other end to do that. In file included from glsl_symbol_table.cpp:26:0: ast.h:339:35: warning: type qualifiers ignored on function return type [-Wignored-qualifiers] const bool is_single_dimension() ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Allow indirect GS input indexing in the scalar backend.Kenneth Graunke2015-11-184-46/+107
| | | | | | | | | | | | | | | | | | This allows arbitrary non-constant indices on GS input arrays, both for the vertex index, and any array offsets beyond that. All indirects are handled via the pull model. We could potentially handle indirect addressing of pushed data as well, but it would add additional code complexity, and we usually have to pull inputs anyway due to the sheer volume of input data. Plus, marking pushed inputs as live due to indirect addressing could exacerbate register pressure problems pretty badly. We'd need to be careful. v2: Use updated MOV_INDIRECT opcode. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Abdiel Janulgue <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* gallium/hud: document GALLIUM_HUD_PERIOD in envvars.html.Jimmy Berry2015-11-191-0/+2
| | | | Signed-off-by: Marek Olšák <[email protected]>
* gallium/hud: control visibility at startup and runtime.Jimmy Berry2015-11-192-0/+35
| | | | | | | - env GALLIUM_HUD_VISIBLE: control default visibility - env GALLIUM_HUD_SIGNAL_TOGGLE: toggle visibility via signal Signed-off-by: Marek Olšák <[email protected]>
* i965/nir: Add hooks for testing nir_shader_cloneJason Ekstrand2015-11-181-9/+26
| | | | | | | | | | This commit adds code for testing nir_shader_clone by running it after each and every optimization pass and throwing away the old shader. Testing nir_shader_clone is hidden behind a new INTEL_CLONE_NIR environment variable. Reviewed-by: Rob Clark <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* nir: Add support for cloning shadersJason Ekstrand2015-11-184-0/+682
| | | | | | | | This commit is heavily based on one by Rob Clark <[email protected]> but reworked to re-use nir_create functions and do less hashing. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* i965/nir: Validate that NIR passes call nir_metadata_preserve().Kenneth Graunke2015-11-183-3/+48
| | | | | | | | | | | | | | | | | | | | | Failing to call nir_metadata_preserve() can have nasty consequences: some pass breaks dominance information, but leaves it marked as valid, causing some subsequent pass to go haywire and probably crash. This pass adds a simple validation mechanism to ensure passes handle this properly. We add a new bogus metadata flag that isn't used for anything in particular, set it before each pass, and ensure it *isn't* still set after the pass. nir_metadata_preserve will reset the flag, so correct passes will work, and bad passes will assert fail. (I would have made these functions static inline, but nir.h is included in C++, so we can't bit-or enums without lots of casting...) Thanks to Dylan Baker for the idea. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/nir: Add OPT() and OPT_V() macros for invoking NIR passes.Kenneth Graunke2015-11-181-72/+59
| | | | | | | | | | | | | | | | | OPT() is the normal macro for passes that return booleans, while OPT_V() is a variant that works for passes that don't properly report progress. (Such passes should be fixed to return a boolean, eventually.) These macros take care of calling nir_validate_shader() and setting progress appropriately. In the future, it would be easy to add shader dumping similar to INTEL_DEBUG=optimizer by extending the macro. v2 (Jason Ekstrand): - Fix an unused variable warning Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: add array length fieldRob Clark2015-11-182-0/+10
| | | | | | | | This will simplify things somewhat in clone. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: remove nir_variable::max_ifc_array_accessRob Clark2015-11-182-22/+0
| | | | | | | | No users. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* freedreno/a4xx: add fake RGTC support (required for GL3)Rob Clark2015-11-184-2/+23
| | | | | | | | | | The a4xx bits corresponding to 'freedreno/a3xx: add fake RGTC support (required for GL3)' TODO some more r/e.. maybe we get lucky and hw supports some of this directly? For now this will help us enable gl3. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add compressed texture formatsRob Clark2015-11-182-2/+26
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-11-185-11/+37
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: expose GLSL 140 and fake MSAA for GL3.0/3.1 supportIlia Mirkin2015-11-181-2/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix texture buffers, enable offsetsIlia Mirkin2015-11-183-14/+32
| | | | | | | | | | | | | | | The main issue is that the current logic looked into cso->u.tex, which is the wrong side of the union to look into for texture buffers. While I was at it, it was easy enough to add the logic to handle offsets (first_element). - reduce texture buffer size limit (determined experimentally) - don't look at first/last levels, instead look at first/last element - include the first element offset - set offset alignment to 16 (determined experimentally) Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: add support for conditional rendering, required for GL3.0Ilia Mirkin2015-11-187-6/+57
| | | | | | | | | A smarter implementation would make it possible to attach this to emit state for the BY_REGION versions to avoid breaking the tiling. But this is a start. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add fake RGTC support (required for GL3)Ilia Mirkin2015-11-186-27/+176
| | | | | | | | | | | | Also throw in LATC while we're at it (same exact format). This could be made more efficient by keeping a shadow compressed texture to use for returning at map time. However... it's not worth it for now... presumably compressed textures are not updated often. Lastly fix up Z32S8 transfers to non-0 layers. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add missing formats to enable ARB_vertex_type_2_10_10_10_revIlia Mirkin2015-11-183-4/+9
| | | | | | | | | The previously RE'd formats were from an ES driver implementing OES_vertex_type_10_10_10_2 and thus backwards. A future change could add the 2_10_10_10 support. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx+a4xx: fix for stk binning pass hangRob Clark2015-11-183-19/+76
| | | | | | | | | | | | | | We'd end up in a state where shader uses no inputs, yet num_elements is greater than zero. Triggered by a TF vertex shader which did: gl_Position = vec4(0.0, 0.0, 0.0, 0.0); resulting in a binning pass variant with no inputs. Includes equiv fix in a4xx, even though we don't have binning-pass enabled yet on a4xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx+a4xx: fix GL_POINTS lockup w/ GLESRob Clark2015-11-183-6/+11
| | | | | | | | point_size_per_vertex is always TRUE for GLES, causing us to configure the hw as if gl_PointSize was written, even if it was not. Which makes for grumpy hw. Signed-off-by: Rob Clark <[email protected]>
* nir: fix typo in idiv lowering, causing large-udiv-udiv failuresIlia Mirkin2015-11-181-1/+1
| | | | | | | | | | | | | In nv50, and in the python script that Rob circulated, we do: bld.mkCmp(OP_SET, CC_GE, TYPE_U32, (s = bld.getSSA()), TYPE_U32, m, b); Do the same in the nir div lowering pass. This fixes the large-udiv-udiv piglit tests on freedreno. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Signed-off-by: Rob Clark <[email protected]>
* llvmpipe: disable VSX in ppc due to LLVM PPC bugOded Gabbay2015-11-181-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables the use of VSX instructions, as they cause some piglit tests to fail For more details, see: https://llvm.org/bugs/show_bug.cgi?id=25503#c7 With this patch, ppc64le reaches parity with x86-64 as far as piglit test suite is concerned. v2: - Added check that we have at least LLVM 3.4 - Added the LLVM bug URL as a comment in the code v3: - Only disable VSX if Altivec is supported, because if Altivec support is missing, then VSX support doesn't exist anyway. - Change original patch description. Signed-off-by: Oded Gabbay <[email protected]> Cc: "11.0" <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* nvc0/ir: actually emit AFETCH on keplerIlia Mirkin2015-11-181-0/+3
| | | | | | | | Looks like this was forgotten in the commit which added the AFETCH logic. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nir: Store the size of the TCS output patch in nir_shader_info.Kenneth Graunke2015-11-182-0/+9
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add enums for 3DSTATE_TE field values.Kenneth Graunke2015-11-181-0/+28
| | | | | | | | | | | | | 3DSTATE_TE has partitioning, output topology, and domain fields, each of which has several enumerated values. We'll also need to switch on the domain, so enums (rather than #defines) seem like a natural fit. I chose to put these in brw_compiler.h because they'll be stored in struct brw_tes_prog_data, which will live there. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* meta/generate_mipmap: Don't leak the framebuffer objectIan Romanick2015-11-181-0/+5
| | | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: "10.6 11.0" <[email protected]>
* svga: use more VGPU10 formatsBrian Paul2015-11-181-30/+67
| | | | | | | | | | We always want to prefer the VGPU10 formats over the VGPU9 ones when we have VGPU10 support. Original patch by Jose and updated by Brian. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* svga: add/use new svga_sampler_format() functionBrian Paul2015-11-183-0/+30
| | | | | | | | | This is important for the case of sampling from a depth texture. In that case, we need to sample the texture as if it were a single-channel color texture. For other/color formats, we can use the format as-is. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* radeon: count cs dwords separately for query begin and endNicolai Hähnle2015-11-182-15/+21
| | | | | | This will be important for perfcounter queries. Reviewed-by: Marek Olšák <[email protected]>
* radeon: expose r600_query_hw functions for reuseNicolai Hähnle2015-11-182-14/+27
| | | | | Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: implement r600_query_hw_get_result via function pointersNicolai Hähnle2015-11-182-99/+94
| | | | | | We will need the clear_result override for the batch query implementation. Reviewed-by: Marek Olšák <[email protected]>
* radeon: split hw query buffer handling from cs emitNicolai Hähnle2015-11-182-81/+133
| | | | | | | | | The idea here is that driver queries implemented outside of common code will use the same query buffer handling with different logic for starting and stopping the corresponding counters. Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: convert hardware queries to the new styleNicolai Hähnle2015-11-182-148/+172
| | | | | | | | | Move r600_query and r600_query_hw into the header because we will want to reuse the buffer handling and suspend/resume logic outside of the common radeon code. Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: convert software queries to the new styleNicolai Hähnle2015-11-181-172/+194
| | | | | | | | Software queries are all queries that do not require suspend/resume and explicit handling of result buffers. Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: add query handler function pointersNicolai Hähnle2015-11-182-7/+62
| | | | | | | | The goal here is to be able to move the implementation details of hardware- specific queries (in particular, performance counters) out of the common code. Reviewed-by: Marek Olšák <[email protected]> [Fixed a rebase conflict and re-tested before pushing.]
* radeon: move R600_QUERY_* constants into a new query header fileNicolai Hähnle2015-11-184-15/+51
| | | | | | | More query-related structures will have to be moved into their own header file to support hardware-specific performance counters. Reviewed-by: Marek Olšák <[email protected]>
* radeon: cleanup driver query listNicolai Hähnle2015-11-181-29/+55
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon: move get_driver_query_info to r600_query.cNicolai Hähnle2015-11-183-45/+51
| | | | Reviewed-by: Marek Olšák <[email protected]>
* i965: Prevent fast clears for MSRTs on SKLNeil Roberts2015-11-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | There are currently a bunch of formats that behave strangely when sampling the cleared color from the MCS buffer on SKL. They seem to mostly be formats that don't have an alpha component, although it's not all of them, and we haven't yet found anything in the specs which would explain this. For now to be on the safe side this patch just prevents fast clears for MSRTs on SKL altogether so that when fast clears are eventually enabled it will only be for single-sampled surfaces. The assumption is that clears are probably more likely to be used in single-sampled applications anyway so we can at least get them working and we can enable MSRTs later once we understand the problem better. This patch should have no functional effect other than perhaps receiving fewer perf_debug messages on SKL+. v2: Improve the commit message to avoid saying the patch disables fast clears because it will be merged before fast clears are enabled for any surfaces so it doesn't actually disable anything. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* vc4: Don't bother lowering uniforms when the same value is used twice.Eric Anholt2015-11-171-13/+33
| | | | | | | | | | | | | DEQP likes to do math on uniforms, and the "fmaxabs dst, uni, uni" to get the absolute value would get lowered. The lowering doesn't bother to try to restrict the lifetime of the lowered uniforms, so we'd end up register allocation failng due to this on 5 of the tests (More tests still fail in RA, which look like we'll need to reduce lowered uniform lifetimes to fix). No changes on shader-db, though fewer extra MOVs are generated on even glxgears (MOVs pair well enough that it ends up being the same instruction count).
* vc4: Fix uniform reordering to support reading the same uniform twice.Eric Anholt2015-11-171-8/+18
| | | | | This does actually happen in the wild (particularly fabs of a uniform), so we'd like to support it.
* vc4: Fix documentation on vc4_qir_lower_uniforms.c.Eric Anholt2015-11-171-7/+3
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* vc4: Add support for nir_op_uge, using the carry bit on QPU_A_SUB.Eric Anholt2015-11-175-0/+26
| | | | | | | | It looks like nir_lower_idiv is going to use it soon, so add support. With Ilia's change, this fixes one case in fs-op-div-large-uint-uint (with GL 3.0 forced on). Cc: "11.0" <[email protected]>
* i965: Fix PIPE_CONTOL typo.Kenneth Graunke2015-11-171-1/+1
| | | | PIPE_CONTOL!!!
* i965: Add assertion for src_stencil payload sizeBen Widawsky2015-11-171-0/+6
| | | | | | | | | | This helps address a coverity warning and prevents future questions about this code. Reported-by: Coverity (via Ilia) Cc: Ilia Mirkin <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Implement ARB_pipeline_statistics_query tessellation counters.Kenneth Graunke2015-11-171-8/+8
| | | | | | | | | | We basically just need to uncomment Ben's code. v2: Fix obvious bugs caught by Ben. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* glsl: rename location layout helperTimothy Arceri2015-11-181-5/+5
| | | | | | | Change name from validate -> apply to more accurately describe what the function does. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
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