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* radeonsi: emit_cb_render_state packets optimizationSonny Jiang2018-06-073-9/+48
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_db_render_state packets optimizationSonny Jiang2018-06-075-29/+95
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* drisw: Fix invalid pointer arithmeticJan Vesely2018-06-071-1/+1
| | | | | | | | Use of void * in pointer arithmetic is illegal, use char * instead. Fixes: cf54bd5e8381dba18d52fe438acda20cc1685bf3 ("drisw: use shared memory when possible") Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Jan Vesely <[email protected]>
* radeonsi: fix possible truncation on renderer stringTimothy Arceri2018-06-081-1/+1
| | | | | | | Fixes truncation warning in gcc 8.1 Fixes: 8539c9bf3158 ("gallium/radeon: add the kernel version into the renderer string") Reviewed-by: Michel Dänzer <[email protected]>
* ac: fix possible truncation of intrinsic nameTimothy Arceri2018-06-081-1/+1
| | | | | | | | Fixes the gcc warning: snprintf’ output between 26 and 33 bytes into a destination of size 32 Fixes: d5f7ebda3ec0 ("ac: add LLVM build functions for subgroup instrinsics") Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: Fix number of coords for getlod.Bas Nieuwenhuizen2018-06-071-3/+18
| | | | | | | | | | The LLVM 6 code reduced it to a non-array call. We need to do that with the new code too. This fixes dEQP-VK.glsl.texture_functions.query.texturequerylod.*array* for radv. Fixes: a9a79934412 "amd/common: use the dimension-aware image intrinsics on LLVM 7+" Reviewed-by: Dave Airlie <[email protected]>
* features: add virgl to the GL features listDave Airlie2018-06-081-40/+40
| | | | | | | | | | | | | This hopefully adds virgl to the correct places and current statuses of various extensions. virgl of course relies on two external things a) host driver that can support the features b) up to date host virglrenderer library that can support the features. This list will be maintained as latest (a) + (b) + mesa. Reviewed-by: Gurchetan Singh <[email protected]>
* meson: Add support for read-only text segment on x86Matt Turner2018-06-072-0/+11
| | | | | | | Port of 6dfc5e28f7d0 (configure.ac: Add support to enable read-only text segment on x86.) to Meson. Reviewed-by: Dylan Baker <[email protected]>
* meson: work around gentoo applying -m32 to host compiler in cross buildsDylan Baker2018-06-071-1/+4
| | | | | | | | | | | Gentoo's ebuild system always adds -m32 to the compiler for doing x86_64 -> x86 cross builds, while meson expects it not to do that. This results in an x86 -> x86 cross build, and assembly gets disabled. Fixes: 2d62fc06465281d3d45b8a7c7fd2b17ef718448c ("meson: disable x86 asm in fewer cases.") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/screen: Sanity check that all formats we advertise are useableJason Ekstrand2018-06-071-4/+20
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/screen: Use RGBA non-sRGB formats for imagesJason Ekstrand2018-06-071-0/+9
| | | | | | | | | | Not all of the MESA_FORMAT and ISL_FORMAT helpers we use can properly handle RGBX formats. Also, we don't want to make decisions based on those in the first place because we can't render to RGBA and we use the non-sRGB version to determine whether or not to allow CCS_E. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/screen: Return false for unsupported formats in query_modifiersJason Ekstrand2018-06-071-2/+14
| | | | | Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/screen: Refactor query_dma_buf_formatsJason Ekstrand2018-06-071-12/+13
| | | | | | | | | This reworks it to work like query_dma_buf_modifiers and, in particular, makes it more flexible so that we can disallow a non-static set of formats. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add bounds-checking assertions for the format_info tableJason Ekstrand2018-06-071-8/+16
| | | | | | | | | | | We follow the same convention as isl_format_get_layout in having two assertions to ensure that only valid formats are passed in. We also check against the array size of the table because some valid formats such as CCS formats will may be past the end of the table. This fixes some potential out-of-bounds array access even in valid cases. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add bounds-checking assertions in isl_format_get_layoutJason Ekstrand2018-06-072-12/+22
| | | | | | | | | | | | We add two assertions instead of one because the first assertion that format != ISL_FORMAT_UNSUPPORTED is more descriptive and checks for a real but unsupported enumerant while the second ensures that they don't pass in garbage values. We also update some other helpers to use isl_format_get_layout instead of using the table directly so that they get bounds checking too. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* meson: Clarify why asm cannot be used in cross compileDylan Baker2018-06-071-7/+17
| | | | | | | | | | This makes the reasoning for why a cross compile is not using asm clearer (hopefully). v2: - fix typos Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* docs: talk about Wayland instead of libwaylandEric Engestrom2018-06-071-2/+2
| | | | | Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* anv: Set fence/semaphore types to NONE in impl_cleanupJason Ekstrand2018-06-071-13/+16
| | | | | | | | | | There were some places that were calling anv_semaphore_impl_cleanup and neither deleting the semaphore nor setting the type back to NONE. Just set it to NONE in impl_cleanup to avoid these issues. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106643 Fixes: 031f57eba "anv: Add a basic implementation of VK_KHX_external..." Reviewed-by: Lionel Landwerlin <[email protected]>
* nir: Add global invocation id intrinsic.Plamena Manolova2018-06-072-0/+5
| | | | | | | | Add the missing nir intrinsic for the gl_GlobalInvocationID compute shader variable. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* travis: bump libwayland to the first version with libwayland-eglEric Engestrom2018-06-071-1/+1
| | | | | Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* i965: Require softpin support for Cannonlake and later.Kenneth Graunke2018-06-061-0/+10
| | | | | | | | | | | This isn't strictly necessary, but anyone running Cannonlake will already have Kernel 4.5 or later, so there's no reason to support the relocation model on Gen10+. This will let us avoid dealing with them for new features. Reviewed-by: Scott D Phillips <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Allocate VMA in userspace for full-PPGTT systems.Kenneth Graunke2018-06-061-1/+1
| | | | | | | | | | | | | | | | This patch enables soft-pinning of all buffers, allowing us to skip relocation processing entirely. All systems with full PPGTT and > 4GB of VMA should gain these benefits. This should be most Gen8+. Unfortunately, this excludes a few systems: - Cherryview (only has 32-bit addressing, despite 48-bit pointers) - Broadwell with a 32-bit kernel - Anybody running pre-4.5 kernel. We may enable it for Cherryview in the future, but it would require some tweaks to the memory zone. Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Emit VF cache invalidates for 48-bit bugs with softpin.Kenneth Graunke2018-06-063-5/+51
| | | | | | | | | | | | | | | | | | commit 92f01fc5f914fd500497d0c3aed75f3ac8dc054d made i965 start emitting VF cache invalidates when the high bits of vertex buffers change. But we were not tracking vertex buffers emitted by BLORP. This was papered over by a mistake where I emitted VF cache invalidates all the time, which Chris fixed in commit 3ac5fbadfd8644d30fce9ff267cb811ad157996a. This patch adds a new hook which allows the driver to track addresses and request a VF cache invalidate as appropriate. v2: Make the driver do the PIPE_CONTROL so it can apply workarounds (caught by Jason Ekstrand). Rebase on anv bug fix. v3: Don't screw up the boolean (caught by Jason Ekstrand). Fixes: 92f01fc5f914 ("i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.") Reviewed-by: Jason Ekstrand <[email protected]>
* nir: add opt_if_loop_terminator()Timothy Arceri2018-06-071-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | This pass detects potential loop terminators and moves intructions from the non breaking branch after the if-statement. This enables both the new opt_if_simplification() pass and loop unrolling to potentially progress further. Unexpectedly this change speed up shader-db run times by ~3% Ivy Bridge shader-db results (all changes in dolphin/ubershaders): total instructions in shared programs: 9995662 -> 9995338 (-0.00%) instructions in affected programs: 87845 -> 87521 (-0.37%) helped: 27 HURT: 0 total cycles in shared programs: 230931495 -> 230925015 (-0.00%) cycles in affected programs: 56391385 -> 56384905 (-0.01%) helped: 27 HURT: 0 Reviewed-by: Ian Romanick <[email protected]>
* nir: move ends_in_break() helper to nir_loop_analyze.hTimothy Arceri2018-06-072-13/+13
| | | | | | | We will use the helper while simplifying potential loop terminators in the following patch. Reviewed-by: Ian Romanick <[email protected]>
* radv: fix Coverity no effect control flow issueTimothy Arceri2018-06-071-1/+1
| | | | | swizzle is unsigned so "desc->swizzle[c] < 0" is never true. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* intel/blorp: Don't vertex fetch directly from clear valuesJason Ekstrand2018-06-061-44/+41
| | | | | | | | | | | | | | On gen8+, we have to VF cache flush whenever a vertex binding aliases a previous binding at the same index modulo 4GiB. We deal with this in Vulkan by ensuring that vertex buffers and the dynamic state (from which BLORP pulls its vertex buffers) are in the same 4GiB region of the address space. That doesn't work if we're reading clear colors with the VF unit. In order to work around this we switch to using MI commands to copy the clear value into the vertex buffer we allocate for the normal constant data. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* dri: add missing 16bits formats mappingLionel Landwerlin2018-06-071-0/+16
| | | | | | | | | | | | | | | | | | i965 advertises the 16-bit R and RG formats through eglQueryDmaBufFormatsEXT but falls over when a client tries to use or asks more information about such a format because driImageFormatToGLFormat returns MESA_FORMAT_NONE. Found by Eero Tamminen. v2: Add G16R16 formats (Lionel) v3: Fix G16R16 mapping to mesa format (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642 Reviewed-by: Plamena Manolova <[email protected]> (v2) Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Look into uniform structs for samplers when counting num_textures.Eric Anholt2018-06-061-12/+44
| | | | | | | | | | | | | | mesa/st decides whether to update samplers after a program change based on whether num_textures is nonzero. By not counting samplers in a uniform struct, we would segfault in KHR-GLES3.shaders.struct.uniform.sampler_vertex if it was run in the same context after a non-vertex-shader-uniform testcase (as is the case during a full conformance run). v2: Implement using two separate pure functions instead of updating pointers. Reviewed-by: Jason Ekstrand <[email protected]>
* v3d: Work around GFXH-1461/GFXH-1689 by using CLEAR_TILE_BUFFERS.Eric Anholt2018-06-061-10/+17
| | | | | | | This doesn't seem to have done anything to my test results. However, given that we've still got a class of GPU hangs, following the workarounds that the closed driver does so that we get the same command sequences seems like a good idea.
* v3d: Enable the new NIR bitfield operation lowering paths.Eric Anholt2018-06-061-2/+19
| | | | | | | | | | These together get the GLSL 3.00 unorm/snorm pack functions and MESA_shader_integer operations working. v2: Fix commit message typo. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: Add lowering for nir_op_bit_count.Eric Anholt2018-06-062-0/+38
| | | | | | | | | This is basically the same as the GLSL lowering path. v2: Fix typo in the link Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: Add lowering for nir_op_bitfield_reverse.Eric Anholt2018-06-062-1/+48
| | | | | | | This is basically the same as the GLSL lowering path. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: Add an ALU lowering pass for mul_high.Eric Anholt2018-06-065-0/+171
| | | | | | | | This is based on the glsl/lower_instructions.cpp implementation, but should be much more readable. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: Add lowering for find_lsb.Eric Anholt2018-06-062-0/+6
| | | | | | | There is a fairly simple relation to turn this into ufind_msb. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: Add lowering for ifind_msb to ufind_msb.Eric Anholt2018-06-062-0/+6
| | | | | | | | ufind_msb is easily expressed in terms of clz, and we can reduce ifind_msb to that. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: Add lowering from ibitfield_extract/ubitfield_extract to shifts.Eric Anholt2018-06-062-0/+19
| | | | | | | | V3D doesn't have opcodes for ibfe/ubfe, so we need to lower similarly to glsl/lower_instructions.cpp. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: Add lowering for bitfieldInsert without using bfi.Eric Anholt2018-06-062-0/+19
| | | | | | | | | | | If you don't have HW to do bfi, then lowering bitfieldInsert to bfi makes things harder than keeping the "bits" argument around. This still uses bfm, but I've added the obvious lowering of bfm if you need it. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* docs: add note about moving to libwayland-egl in 18.2.0Eric Engestrom2018-06-061-0/+8
| | | | | | | | | Cc: Emil Velikov <[email protected]> Cc: Daniel Stone <[email protected]> Cc: Andres Gomez <[email protected]> Cc: Dylan Baker <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* egl: remove wayland-egl now that we're using libwayland-eglEric Engestrom2018-06-067-516/+0
| | | | | | | Cc: Emil Velikov <[email protected]> Cc: Daniel Stone <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* egl: rewire the build systems to use libwayland-eglEric Engestrom2018-06-067-21/+15
| | | | | | | Cc: Emil Velikov <[email protected]> Cc: Daniel Stone <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* glsl: Take 'double' as reserved after GLSL ES 1.0zhaowei yuan2018-06-051-1/+1
| | | | | | | | | GLSL ES 1.0.17 specifies that "double" is a keyword reserved Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106823 Signed-off-by: zhaowei yuan <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r300g/swtcl: make pipe_context uploaders use malloc'd memory as beforeMarek Olšák2018-06-051-3/+6
| | | | | | | | | | Discovered by Roland Scheidegger. The resource_create code uses GPU memory for PIPE_BIND_CUSTOM, but malloc'd memory otherwise. Vertex and index buffers should use malloc'd memory. Cc: 18.0 18.1 <[email protected]>
* intel/eu: Use a struct copy instead of a memcpyJason Ekstrand2018-06-051-1/+1
| | | | | | | | | The memcpy had the wrong size and this was causing crashes on 32-bit builds of the driver. Fixes: 6a9525bf6729a8 "intel/eu: Switch to a logical state stack" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106830 Reviewed-by: Kenneth Graunke <[email protected]>
* radv: Use correct color format for fast clearsPhilip Rebohle2018-06-051-2/+2
| | | | | | | | | Using the image format is incorrect when the view has a different format than the image. Instead, the view format needs to be used. Reviewed-by: Bas Nieuwenhuizen <[email protected]> CC: 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106687
* v3d: Be more explicit about include directory from our generated code.Eric Anholt2018-06-053-2/+5
| | | | | | | You'd need src/broadcom/cle/ in the -I previously, for srcdir != builddir. nir was fine at that, but automake didn't have it. Bugzilla: https://github.com/anholt/mesa/issues/104
* radv: Do not hardcode fast clear formats.Bas Nieuwenhuizen2018-06-051-180/+73
| | | | | | | | except for the odd one out. This should support many more formats. Reviewed-by: Dave Airlie <[email protected]>
* intel/tools: add intel_sanitize_gpu to EXTRA_DISTScott D Phillips2018-06-051-0/+2
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106778 Fixes: cc41603d6d ("intel/tools: new intel_sanitize_gpu tool") Reviewed-by: Dylan Baker <[email protected]>
* util/tests/vma: Fix warning c++11-narrowingScott D Phillips2018-06-051-1/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106801 Fixes: 943fecc569 ("util: Add a randomized test for the virtual memory allocator") Reviewed-by: Dylan Baker <[email protected]>
* util: tests: vma test depends on C++11 supportScott D Phillips2018-06-051-2/+5
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106776 Fixes: 943fecc569 ("util: Add a randomized test for the virtual memory allocator") Tested-by: Vinson Lee <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
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