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* st/mesa: treat 1D ARRAY upload like a depth or 2D array upload.Dave Airlie2011-02-241-0/+12
| | | | | | | | | | | | | This is because the HW doesn't always store a 1D array like a 2D texture, it more likely stores it like 2D texture (i.e. alignments etc). This means we upload each slice separately and let the driver work out where to put it. this might break nvc0 as I can't test it, I have only nv50 here. Signed-off-by: Dave Airlie <[email protected]>
* scons: Fix Cygwin platform names.Vinson Lee2011-02-232-2/+2
| | | | Fixes immediate Python exceptions with SCons on Cygwin.
* i915g: Lazy emit dynamic stateJakob Bornecrantz2011-02-245-40/+36
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* i915g: Lazy emit immediate stateJakob Bornecrantz2011-02-245-55/+59
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* i915g: Disable LIS7 state updates for nowJakob Bornecrantz2011-02-242-1/+5
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* i915g: Clean up in i915_state_immediateJakob Bornecrantz2011-02-241-5/+1
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* i915g: Remove outdated commentJakob Bornecrantz2011-02-241-8/+0
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* i915g: Use dump function in sw winsysJakob Bornecrantz2011-02-241-7/+2
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* i915g: Enable mirror repeat wrap modeJakob Bornecrantz2011-02-243-6/+4
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* i915g: Always set vbo to flush on flushesJakob Bornecrantz2011-02-241-1/+1
| | | | Reported-by Chris Wilson <[email protected]>
* intel: gen3 is particular sensitive to batch sizeChris Wilson2011-02-231-1/+1
| | | | | | | | | | | ... and prefers a small batch whereas gen4+ prefer a large batch to carry more state. Tuning using openarena/padman indicate that a batch size of just 4096 is best for those cases. Bugzilla: https://bugs.freedesktop.org/process_bug.cgi Signed-off-by: Chris Wilson <[email protected]>
* i915: And remember assign the new value to the state reg...Chris Wilson2011-02-231-0/+1
| | | | | | | Fixes regression from 298ebb78de8a6b6edf0aa0fe8d784d00bbc2930e. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34589 Signed-off-by: Chris Wilson <[email protected]>
* Fix GLX_USE_TLS define.Tom Fogal2011-02-231-5/+3
| | | | It was only getting set in the case of DRI drivers.
* r600g: Request DWORD aligned vertex buffers.Fabian Bieler2011-02-231-1/+1
| | | | | | The spec says that the offsets in the vertex-fetch instructions need to be byte-aligned and makes no specification with regard to the required alignment of the offset and stride in the vertex resource constant register. However, testing indicates that all three values need to be DWORD aligned.
* st/mesa: fix computing the lowest address for interleaved attribsWiktor Janas2011-02-231-3/+6
| | | | | | | | | Ptr can be very well NULL, so when there are two arrays, with one having offset 0 (and thus NULL Ptr), and the other having a non-zero offset, the non-zero value is taken as minimum (because of !low_addr ? start ...). On 32-bit systems, this somehow works. On 64-bit systems, it leads to crashes. Signed-off-by: Marek Olšák <[email protected]>
* vbo: added vbo_check_buffers_are_unmapped() debug functionBrian Paul2011-02-222-0/+19
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* vbo: removed unused #defines, add commentsBrian Paul2011-02-221-3/+6
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* mesa: move comment, change debug codeBrian Paul2011-02-221-3/+5
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* vbo: simplify NeedFlush flag clearingBrian Paul2011-02-221-4/+1
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* vbo: use ctx intstead of exec->ctxBrian Paul2011-02-221-8/+8
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* r300g: fix missing initializers warningBrian Paul2011-02-221-2/+4
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* i915g: remove extra semicolonsBrian Paul2011-02-221-3/+3
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* xlib: pass Display pointer to XMesaGarbageCollect()Andy Skinner2011-02-223-7/+7
| | | | | | Fixes an issue when different displays are used on different threads. Signed-off-by: Brian Paul <[email protected]>
* i965: Increase Sandybridge point size clamp.Kenneth Graunke2011-02-221-1/+1
| | | | | | | | 255.875 matches the hardware documentation. Presumably this was a typo. Found by inspection. Not known to fix any issues. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.Kenneth Graunke2011-02-221-1/+1
| | | | | | | | pixel_w is the final result; wpos_w is used on gen4 to compute it. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Refactor control flow stack handling.Kenneth Graunke2011-02-221-7/+27
| | | | | | | | | We can't safely use fixed size arrays since Gen6+ supports unlimited nesting of control flow. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Avoid register coalescing away gen6 MATH workarounds.Kenneth Graunke2011-02-221-0/+10
| | | | | | | | | | | | | The code that generates MATH instructions attempts to work around the hardware ignoring source modifiers (abs and negate) by emitting moves into temporaries. Unfortunately, this pass coalesced those registers, restoring the original problem. Avoid doing that. Fixes several OpenGL ES2 conformance failures on Sandybridge. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Apply source modifier workarounds to POW as well.Kenneth Graunke2011-02-221-3/+7
| | | | | | | | | | Single-operand math already had these workarounds, but POW (the only two operand function) did not. It needs them too - otherwise we can hit assertion failures in brw_eu_emit.c when code is actually generated. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix shaders that write to gl_PointSize on Sandybridge.Kenneth Graunke2011-02-221-0/+2
| | | | | | | | | gl_PointSize (VERT_RESULT_PSIZ) doesn't take up a message register, as it's part of the header. Without this fix, writing to gl_PointSize would cause the SF to read and use the wrong attributes, leading to all kinds of random looking failure. Reviewed-by: Eric Anholt <[email protected]>
* mesa: Avoid undeclared ffs function warning on mingw.José Fonseca2011-02-221-0/+6
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* gallium: s/PIPE_TRANSFER_CPU_READ/PIPE_TRANSFER_READ/ in comments.José Fonseca2011-02-221-4/+4
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* gallium/docs: Update PIPE_TRANSFER_xx docs. Reformat to use definitions.José Fonseca2011-02-221-13/+29
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* gallium: new transfer flag: DISCARD_WHOLE_RESOURCEKeith Whitwell2011-02-221-3/+18
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* st/mesa: fix crash when using both user and vbo buffers with the same strideMarek Olšák2011-02-201-0/+8
| | | | | | | | | If two buffers had the same stride where one buffer is a user one and the other is a vbo, it was considered to be one interleaved buffer, resulting in incorrect rendering and crashes. This patch makes sure that the interleaved buffer is either user or vbo, not both.
* st/mesa: fix crash when DrawBuffer->_ColorDrawBuffers[0] is NULLMarek Olšák2011-02-201-6/+10
| | | | This fixes the game Tiny and Big.
* i965: Trim the interleaved upload to the minimum number of verticesChris Wilson2011-02-221-1/+5
| | | | | | ... should have no impact on a properly formatted draw operation. Signed-off-by: Chris Wilson <[email protected]>
* i965: Reinstate max-index paranoiaChris Wilson2011-02-221-1/+1
| | | | | | | Don't trust the applications not to reference beyond the end of the vertex buffers. Signed-off-by: Chris Wilson <[email protected]>
* i965: Zero the offset into the vbo when uploading non-interleavedChris Wilson2011-02-221-0/+1
| | | | | | Fixes regression from 559435d9152acc7162e4e60aae6591c7c6c8274b. Signed-off-by: Chris Wilson <[email protected]>
* st/dri: Track drawable context bindingsJakob Bornecrantz2011-02-204-2/+14
| | | | | | | | | | | | | | | | | | | Needs to track this ourself since because we get into a race condition with the dri_util.c code on make current when rendering to the front buffer. This is what happens: Old context is rendering to the front buffer. App calls MakeCurrent with a new context. dri_util.c sets drawable->driContextPriv to the new context and then calls the driver make current. st/dri make current flushes the old context, which calls back into st/dri via the flush frontbuffer hook. st/dri calls dri loader flush frontbuffer, which calls invalidate buffer on the drawable into st/dri. This is where things gets wrong. st/dri grabs the context from the dri drawable (which now points to the new context) and calls invalidate framebuffer to the new context which has not yet set the new drawable as its framebuffers since we have not called make current yet, it asserts.
* i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.Eric Anholt2011-02-211-1/+1
| | | | Fixes regression in scissor-stencil-clear and 5 other tests.
* Revert "mesa: convert macros to inline functions"Brian Paul2011-02-211-22/+22
| | | | | | This reverts commit e9ff76aa81d9bd973d46b7e46f1e4ece2112a5b7. Need to use macros so __FUNCTION__ reports the caller.
* st/mesa: need to translate clear color according to surface's base formatBrian Paul2011-02-214-47/+75
| | | | | | | | | | | When clearing a GL_LUMINANCE_ALPHA buffer, for example, we need to convert the clear color (R,G,B,A) to (R,R,R,A). We were doing this for texture border colors but not renderbuffers. Move the translation function to st_format.c and share it. This fixes the piglit fbo-clear-formats test. NOTE: This is a candidate for the 7.9 and 7.10 branches.
* st/mesa: fix the default case in st_format_datatype()Brian Paul2011-02-211-5/+2
| | | | | | Part of the fix for piglit fbo-clear-formats NOTE: This is a candidate for the 7.9 and 7.10 branches.
* i915g: add some throttlingDaniel Vetter2011-02-211-0/+9
| | | | | | Intel classic drivers switched to this, too, so it must be good. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: s/bool/boolean/ style-fixup in winsysDaniel Vetter2011-02-213-3/+4
| | | | Signed-off-by: Daniel Vetter <[email protected]>
* i915g: Fix warningJakob Bornecrantz2011-02-211-1/+0
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* i915g: Add option to lie about capsJakob Bornecrantz2011-02-213-1/+9
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* i915g: Move debug fields to screenJakob Bornecrantz2011-02-214-4/+7
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* i915g: Use debug get once optionsJakob Bornecrantz2011-02-212-3/+9
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* i915g: Rework texture tiling a bitJakob Bornecrantz2011-02-211-14/+8
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