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* r300g: use memset for clearing the shader keyMarek Olšák2015-03-091-1/+2
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* r300g: remove the broken SNORM->UNORM shader lowering passMarek Olšák2015-03-093-54/+0
| | | | Not used anymore.
* r300g: fix RGTC1 and LATC1 SNORM formatsMarek Olšák2015-03-092-31/+17
| | | | Cc: 10.5 10.4 <[email protected]>
* r300g: Fix the ATI1N swizzle (RGTC1 and LATC1)Stefan Dösinger2015-03-091-1/+3
| | | | | | | | | | | | | | | | | | | | | This fixes the GL_COMPRESSED_RED_RGTC1 part of piglit's rgtc-teximage-01 test as well as the precision part of Wine's 3dc format test (fd.o bug 89156). The Z component seems to contain a lower precision version of the result, probably a temporary value from the decompression computation. The Y and W component contain different data that depends on the input values as well, but I could not make sense of them (Not that I tried very hard). GL_COMPRESSED_SIGNED_RED_RGTC1 still seems to have precision problems in piglit, and both formats are affected by a compiler bug if they're sampled by the shader with a swizzle other than .xyzw. Wine uses .xxxx, which returns random garbage. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89156 Signed-off-by: Marek Olšák <[email protected]> Cc: 10.5 10.4 <[email protected]>
* radeonsi: Add additional information to shader dumpsTom Stellard2015-03-091-6/+12
| | | | | | | This adds SGPR count, VGPR count, shader size, LDS size, and scratch usage to shader dumps. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/compute: Use value from compiler for COMPUTE_PGM_RSRC1.FLOAT_MODETom Stellard2015-03-093-1/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* clover: Return the minimum required value for CL_DEVICE_SINGLE_FP_CONFIG v2Tom Stellard2015-03-091-1/+4
| | | | | | | | | | This means dropping CL_FP_DENORM from the current return value. v2: - Add comments about minimum values for OpenCL 1.2. Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jan Vesely <[email protected]>
* freedreno/ir3: get the # of miplevels from getinfoIlia Mirkin2015-03-091-0/+20
| | | | | | | | | This fixes ARB_texture_query_levels to actually return the desired value. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Cc: "10.4 10.5" <[email protected]>
* freedreno/ir3: fix array count returned by TXQIlia Mirkin2015-03-091-2/+42
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Cc: "10.4 10.5" <[email protected]>
* freedreno: move fb state copy after checking for size changeIlia Mirkin2015-03-091-2/+2
| | | | | | | Fixes: 1f3ca56b ("freedreno: use util_copy_framebuffer_state()") Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Cc: "10.4 10.5" <[email protected]>
* nir: Make the printer include nir_variable::location too.Kenneth Graunke2015-03-091-1/+1
| | | | | | | | | Being able to see both location and driver_location can be useful when debugging IO mistakes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965/fs: Implement SIMD16 dual source blending.Iago Toral Quiroga2015-03-095-19/+83
| | | | | | | | | | | | From the SNB PRM, volume 4, part 1, page 193: "The dual source render target messages only have SIMD8 forms due to maximum message length limitations. SIMD16 pixel shaders must send two of these messages to cover all of the pixels. Each message contains two colors (4 channels each) for each pixel in the message payload." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82831 Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Only do gl_FrontFacing workaround in glsl_to_nir for the FS.Kenneth Graunke2015-03-081-1/+2
| | | | | | | | | | | | Vertex shaders can have shader inputs where location happens to be VARYING_SLOT_FACE. Without predicating this on the shader stage, we suddenly end up with load_front_face intrinsics in vertex shaders, which is nonsensical. Fixes spec/arb_vertex_buffer_object/pos-array when using NIR for VS. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Plumb the shader stage into glsl_to_nir().Kenneth Graunke2015-03-083-8/+10
| | | | | | | | | The next commit needs to know the shader stage in glsl_to_nir(). To facilitate that, we pass the gl_shader rather than the raw exec_list of instructions. This has both the exec_list and the stage. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add native_integers to nir_shader_compiler_options.Kenneth Graunke2015-03-085-9/+16
| | | | | | | | | | | glsl_to_nir, tgsi_to_nir, and prog_to_nir all want to know whether the driver supports native integers. Presumably other passes may as well. Adding this to nir_shader_compiler_options is an easy way to provide that information, as it's accessible via nir_shader::options. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Try to make sense of the nir_shader_compiler_options code.Kenneth Graunke2015-03-085-30/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | The code in glsl_to_nir is entirely dead, as we translate from GLSL to NIR at link time, when there isn't a _mesa_glsl_parse_state to pass, so every caller passes NULL. glsl_to_nir seems like the wrong place to try and create the shader compiler options structure anyway - tgsi_to_nir, prog_to_nir, and other translators all would have to duplicate that code. The driver should set this up once with whatever settings it wants, and pass it in. Eric also added a NirOptions field to ctx->Const.ShaderCompilerOptions[] and left a comment saying: "The memory for the options is expected to be kept in a single static copy by the driver." This suggests the plan was to do exactly that. That pointer was not marked const, however, and the dead code used a mix of static structures and ralloced ones. This patch deletes the dead code in glsl_to_nir, instead making it take the shader compiler options as a mandatory argument. It creates an (empty) options struct in the i965 driver, and makes NirOptions point to that. It marks the pointer const so that we can actually do so without generating "discards const qualifier" compiler warnings. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: Delete nir_shader::user_structures and num_user_structures.Kenneth Graunke2015-03-084-22/+0
| | | | | | | | | | | Nothing actually uses these, and the only caller of glsl_to_nir() (brw_fs_nir.cpp) always passes NULL for the _mesa_glsl_parse_state pointer, meaning they'll always be NULL and 0, respectively. Just delete them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Mark array access when copying to a temporary for the ?: operator.Kenneth Graunke2015-03-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Piglit's spec/glsl-1.20/compiler/structure-and-array-operations/ array-selection.vert test contains the following code: gl_Position = (pick_from_a_or_b ? a : b)[i]; where "a" and "b" are uniform vec4[2] variables. ast_to_hir creates a temporary vec4[2] variable, conditional_tmp, and generates an if-block to copy one or the other: (declare (temporary) (array vec4 2) conditional_tmp) (if (var_ref pick_from_a_or_b) ((assign () (var_ref conditional_tmp) (var_ref a))) ((assign () (var_ref conditional_tmp) (var_ref b)))) However, we failed to update max_array_access for "a" and "b", so it remained 0 - here, the whole array is being accessed. At link time, update_array_sizes() used this bogus information to change the types of "a" and "b" to vec4[1]. We then had assignments from a vec4[1] to a vec4[2], which is highly illegal. This tripped assertions in nir_split_var_copies with scalar VS. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: [email protected]
* i965/nir: Resolve source modifiers on Gen8+ logic operations.Kenneth Graunke2015-03-083-0/+27
| | | | | | | | | | | On Gen8+, AND/OR/XOR/NOT don't support the abs() source modifier, and negate changes meaning to bitwise-not (~, not -). This isn't what NIR expects, so we should resolve the source modifers via a MOV. +30 Piglits (fs-op-bit{and,or,xor}-not-abs-*). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* st/mesa: drop unused texture functionDave Airlie2015-03-092-50/+0
| | | | | | | This has no users. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/st: remove unused TexDataDave Airlie2015-03-092-27/+0
| | | | | | | | | | this isn't hooked up to anything at all from what I can see. Seems like a left over from commit 5d67d4fbebb(st/mesa: remove st_TexImage(), use core Mesa code instead). Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno: replace glsl130 debug flag with glsl120Rob Clark2015-03-082-12/+10
| | | | | | | | | | | | | | Now that relative-dst works, we should never fall back to the old compiler. (Which is almost true, other than a couple edge case sched fails in piglit). So replace glsl130 flag to force GLSL 130 and integers on a3xx/a4xx with a glsl120 flag to force GLSL 120 and !integers. If this commit breaks any game/app/etc use FD_MESA_DEBUG=glsl120 as a workaround and please let me know. Signed-off-by: Rob Clark <[email protected]>
* gallium/docs: add some freedreno compiler docsRob Clark2015-03-086-1/+457
| | | | | | | | | | | | | | | Enable the 'sphinx.ext.graphviz' extension, and add in a section for driver specific docs, with freedreno compiler docs beneath. The goal is for more complete compiler docs, and hopefully some docs about other parts of the driver (such as how tiling works, etc). Note that there is also a Distribution -> Drivers section. Although that appears to be simply just a list of drivers. Not sure if that should move under the 'Drivers' section or left alone. I did add a one-line section for freedreno in the existing Distribution -> Drivers section. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: relative dstRob Clark2015-03-085-42/+244
| | | | | | | | | To simplify RA, assign arrays that are written to first. Since enough dependency information is in the graph to preserve order of reads and writes of array, so all SSA names for the array collapse into one, just assign the entire thing by array-id. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out array_fanin() helperRob Clark2015-03-081-17/+30
| | | | | | We'll need this too for relative dst.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop deref nodesRob Clark2015-03-087-80/+53
| | | | | | | | | | | | | | | | | | | | | The meta-deref instruction doesn't really do what we need for relative destination. Instead, since each instruction can reference at most a single address value, track the dependency on the address register via instr->address. This lets us express the dependency regardless of whether it is used for dst and/or src. The foreach_ssa_src{_n} iterator macros now also iterates the address register so, at least in SSA form, the address register behaves as an additional virtual src to the instruction. Which is pretty much what we want, as far as scheduling/etc. TODO: For now, the foreach_src{_n} iterators are unchanged. We could wrap the address in an ir3_register and make the foreach_src_{_n} iterators behave the same way. But that seems unnecessary at this point, since we mainly care about the address dependency when in SSA form. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: helpful iterator macrosRob Clark2015-03-089-111/+109
| | | | | | | | | I remembered that we are using c99.. which makes some sugary iterator macros easier. So introduce iterator macros to iterate all src registers and all SSA src instructions. The _n variants also return the src #, since there are a handful of places that need this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix register usage calculationsRob Clark2015-03-081-7/+14
| | | | | | | | | For cat1 instructions, use reg() as well for relative src, to ensure proper accounting of register usage. Also, for relative instructions, use reg->size rather than reg->wrmask to determine the number of components read/written. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: couple tweaks for cmdline compilerRob Clark2015-03-081-1/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split up ssa_dstRob Clark2015-03-081-17/+25
| | | | | | And a couple other trivial renames, to prepare for relative dst. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix failed assert in groupingRob Clark2015-03-081-27/+44
| | | | | | | | | | | | | | | | | | | | | Turns out there are scenarios where we need to insert mov's in "front" of an input. Triggered by shaders like: VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL SAMP[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyyy 1: MOV TEMP[0].w, IN[1].wwww 2: TXF TEMP[0], TEMP[0], SAMP[0], 1D_ARRAY 3: MOV OUT[1], TEMP[0] 4: MOV OUT[0], IN[0] 5: END Signed-off-by: Rob Clark <[email protected]>
* c99_alloca.h: Also use <alloca.h> for cygwinJon TURNEY2015-03-071-1/+1
| | | | | Signed-off-by: Jon TURNEY <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i915: Fix GCC unused-variable warning in release build.Vinson Lee2015-03-061-2/+1
| | | | | | | | | | i915_debug_fp.c: In function ‘i915_disassemble_program’: i915_debug_fp.c:302:11: warning: unused variable ‘size’ [-Wunused-variable] GLuint size = program[0] & 0x1ff; ^ Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* r300g: Fix build, invalid extern "C" around header inclusion.Mark Janes2015-03-061-0/+8
| | | | | | | | | | | | A previous patch to fix header inclusion within extern "C" neglected to fix the occurences of this pattern in r300 files. When the helper to detect this issue was pushed to master, it broke the build for the r300 driver. This patch fixes the r300 build. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89477 Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* nouveau: Fix build, invalid extern "C" around header inclusion.Mark Janes2015-03-062-2/+7
| | | | | | | | | | | | A previous patch to fix header inclusion within extern "C" neglected to fix the occurences of this pattern in nouveau files. When the helper to detect this issue was pushed to master, it broke the build for the nouveau driver. This patch fixes the nouveau build. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89477 Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* nv50,nvc0: remove bogus 64_FLOAT formatsIlia Mirkin2015-03-061-5/+0
| | | | | | | There is no HW support for these and the VBO pusher doesn't know about them. No need to, either, since the st will be lowering them to 2x32. Signed-off-by: Ilia Mirkin <[email protected]>
* docs: add news item and link release notes for mesa 10.4.6/10.5.0Emil Velikov2015-03-072-0/+15
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: Add sha256 sums for the 10.5.0 releaseEmil Velikov2015-03-071-2/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 0d3e4ed1349565dea8e6c5139400d7441b8ffdca)
* docs: Update 10.5.0 release notesEmil Velikov2015-03-071-2/+145
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 97357d475fc8cbb5dbe7bf17ca41f535827fb253)
* docs: Add sha256 sums for the 10.4.6 releaseEmil Velikov2015-03-071-1/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit fc9dd495b2adbd329d6b58cd611d2acd8ac3070a)
* Add release notes for the 10.4.6 releaseEmil Velikov2015-03-071-0/+141
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 542a754524a2b149c178a2f70c05b292c7228fc2)
* ilo: clarify valid and preferred tilingsChia-I Wu2015-03-072-15/+29
| | | | | We did it right until the switch to gen_surface_tiling, which has GEN8_TILING_W. Generally, GEN8_TILING_W may be valid but not preferred.
* ilo: clean up Gen6 WAsChia-I Wu2015-03-071-34/+62
| | | | | | Add a help function for each WA and make PIPE_CONTROL flags match the WA descriptions. Call gen6_wa_pre_pipe_contro() only before PIPE_CONTROLs. Fix missing gen6_wa_pre_3dstate_vs_toggle() in the rectlist path.
* ilo: add generic ilo_render_3dprimitive()Chia-I Wu2015-03-074-53/+29
| | | | It replaces gen[6-8]_3dprimitive().
* ilo: add generic ilo_render_pipe_control()Chia-I Wu2015-03-075-101/+56
| | | | | It replaces gen[6-8]_pipe_control() and a direct gen6_PIPE_CONTROL() call in ilo_render_emit_flush().
* ilo: fix padding of linear sampler viewsChia-I Wu2015-03-071-4/+2
| | | | Should use the temporary variable in the loop instead of layout->bo_height.
* ilo: do not check for interleaved_samplesChia-I Wu2015-03-071-2/+1
| | | | | interleaved_samples is only zero-initialized when layout_want_mcs() is called. We should not check for it. There is also no need to.
* Revert "egl/main: use c11/threads' mutex directly"Emil Velikov2015-03-0611-47/+111
| | | | | | This reverts commit 6cee785c69a5c8d2d32b6807f9c502117f5a74b0. Not meant to go in yet. Lacking review.
* Revert "egl/main: convert thread management to use c11 threads"Emil Velikov2015-03-061-6/+42
| | | | | | This reverts commit 33eff853363d7eba5e61b00431b95f7aa0d7b0a5. Not meant to go in yet. Lacking review.
* Revert "configure: require pthreads for POSIX builds"Emil Velikov2015-03-061-3/+0
| | | | | | This reverts commit 50714cec2b50c7836841c09f04bfe875de00ae1d. Not meant to go in yet. Lacking review.
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