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gallium_va_encpackedheader01
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Files
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*
i965/vec4: do not split scratch read/write opcodes
Iago Toral Quiroga
2017-01-03
1
-0
/
+9
*
i965/vec4: Do not use DepCtrl with 64-bit instructions
Iago Toral Quiroga
2017-01-03
1
-1
/
+13
*
i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platforms
Iago Toral Quiroga
2017-01-03
1
-3
/
+6
*
i965/vec4: don't copy propagate misaligned registers
Samuel Iglesias Gonsálvez
2017-01-03
1
-0
/
+3
*
i965/vec4: don't propagate single-precision uniforms into 4-wide instructions
Iago Toral Quiroga
2017-01-03
1
-0
/
+11
*
i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions
Iago Toral Quiroga
2017-01-03
1
-0
/
+7
*
i965/vec4: prevent copy-propagation from values with a different type size
Iago Toral Quiroga
2017-01-03
1
-0
/
+7
*
i965/vec4: don't constant propagate 64-bit immediates
Connor Abbott
2017-01-03
1
-0
/
+7
*
i965/vec4: Fix SSBO stores for 64-bit data
Iago Toral Quiroga
2017-01-03
1
-8
/
+32
*
i965/vec4: Fix SSBO loads for 64-bit data
Iago Toral Quiroga
2017-01-03
1
-4
/
+29
*
i965/vec4: Fix UBO loads for 64-bit data
Iago Toral Quiroga
2017-01-03
1
-15
/
+34
*
i965/vec4: Add a shuffle_64bit_data helper
Iago Toral Quiroga
2017-01-03
2
-0
/
+76
*
i965/vec4: support multiple dispatch widths and groups in the IR builder.
Iago Toral Quiroga
2017-01-03
1
-2
/
+37
*
i965/vec4: Lower 64-bit MAD
Iago Toral Quiroga
2017-01-03
2
-0
/
+45
*
i965/vec4/nir: do not emit 64-bit MAD
Iago Toral Quiroga
2017-01-03
1
-5
/
+12
*
i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands
Iago Toral Quiroga
2017-01-03
1
-1
/
+4
*
i965/vec4: fix indentation in pack_uniform_registers
Iago Toral Quiroga
2017-01-03
1
-15
/
+15
*
i965/vec4: fix pack_uniform_registers for doubles
Iago Toral Quiroga
2017-01-03
1
-2
/
+9
*
i965/vec4: teach register coalescing about 64-bit
Iago Toral Quiroga
2017-01-03
1
-3
/
+19
*
i965/disasm: fix subreg for dst in Align16 mode
Iago Toral Quiroga
2017-01-03
1
-1
/
+1
*
i965/vec4: implement access to DF source components Z/W
Iago Toral Quiroga
2017-01-03
1
-0
/
+21
*
i965/vec4: translate 64-bit swizzles to 32-bit
Iago Toral Quiroga
2017-01-03
2
-3
/
+48
*
i965/vec4: add a scalarization pass for double-precision instructions
Iago Toral Quiroga
2017-01-03
2
-0
/
+92
*
i965/vec4: split double-precision SEL
Iago Toral Quiroga
2017-01-03
1
-0
/
+6
*
i965/vec4: teach cmod propagation about different execution sizes
Iago Toral Quiroga
2017-01-03
1
-1
/
+3
*
i965/vec4: teach CSE about exec_size, group and doubles
Iago Toral Quiroga
2017-01-03
1
-7
/
+20
*
i965/disasm: print NibCtrl for instructions with execsize < 8
Iago Toral Quiroga
2017-01-03
1
-1
/
+5
*
i965/vec4: dump NibCtrl for instructions with execsize != 8
Iago Toral Quiroga
2017-01-03
1
-0
/
+3
*
i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions
Iago Toral Quiroga
2017-01-03
1
-0
/
+9
*
i965/vec4: add a SIMD lowering pass
Iago Toral Quiroga
2017-01-03
2
-0
/
+161
*
i965: move the group field from fs_inst to backend_instruction.
Iago Toral Quiroga
2017-01-03
3
-9
/
+10
*
i965/vec4: add a horiz_offset() helper
Iago Toral Quiroga
2017-01-03
1
-0
/
+12
*
i965/vec4: handle 32 and 64 bit channels in liveness analysis
Juan A. Suarez Romero
2017-01-03
5
-53
/
+50
*
i965/vec4: dump the instruction execution size
Iago Toral Quiroga
2017-01-03
1
-1
/
+2
*
i965/vec4: use the IR's execution size
Iago Toral Quiroga
2017-01-03
1
-0
/
+1
*
i965/vec4: fix regs_read() for doubles
Iago Toral Quiroga
2017-01-03
1
-2
/
+2
*
i965/vec4: fix size_written for doubles
Iago Toral Quiroga
2017-01-03
1
-1
/
+2
*
i965: move exec_size from fs_instruction to backend_instruction
Iago Toral Quiroga
2017-01-03
3
-7
/
+8
*
i965/vec4: use the new helper function to create double immediates
Samuel Iglesias Gonsálvez
2017-01-03
1
-1
/
+1
*
i965/vec4: add a helper function to create double immediates
Iago Toral Quiroga
2017-01-03
2
-0
/
+40
*
i965/vec4: fix optimize predicate for doubles
Iago Toral Quiroga
2017-01-03
1
-2
/
+4
*
i965/vec4: implement fsign() for doubles
Iago Toral Quiroga
2017-01-03
1
-15
/
+49
*
i965/vec4: implement d2b
Iago Toral Quiroga
2017-01-03
1
-0
/
+18
*
i965/vec4: implement d2i, d2u, i2d and u2d
Iago Toral Quiroga
2017-01-03
1
-0
/
+14
*
i965/vec4: implement HW workaround for align16 double to float conversion
Iago Toral Quiroga
2017-01-03
1
-0
/
+11
*
i965/vec4: add helpers for conversions to/from doubles
Iago Toral Quiroga
2017-01-03
2
-20
/
+41
*
i965/vec4: Rename DF to/from F generator opcodes
Iago Toral Quiroga
2017-01-03
6
-20
/
+20
*
i965/vec4: fix register allocation for 64-bit undef sources
Iago Toral Quiroga
2017-01-03
1
-1
/
+2
*
i965/vec4: make opt_vector_float ignore doubles
Iago Toral Quiroga
2017-01-03
1
-0
/
+1
*
i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations
Iago Toral Quiroga
2017-01-03
1
-0
/
+4
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