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* gallivm: add PK2H/UP2H supportRoland Scheidegger2016-02-022-7/+9
| | | | | | | | | | | | Add support for these opcodes, the conversion functions were already there albeit need some new packing stuff. Just like the tgsi version, piglit won't like it for all the same reasons, so it's disabled (UP2H passes piglit arb_shader_language_packing tests, albeit since PK2H won't due to those rounding differences I don't know if that one works or not as the piglit test is rather difficult to deal with). Reviewed-by: Brian Paul <[email protected]>
* gallivm: add PK2H/UP2H supportRoland Scheidegger2016-02-025-2/+119
| | | | | | | | | | Add support for these opcodes, the conversion functions were already there albeit need some new packing stuff. Just like the tgsi version, piglit won't like it for all the same reasons, so it's disabled (UP2H passes piglit arb_shader_language_packing tests, albeit since PK2H won't due those rounding differences I don't know if that one works or not as the piglit test is rather difficult to deal with).
* tgsi: add PK2H/UP2H supportRoland Scheidegger2016-02-022-3/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | The util functions handle the half-float conversion. Note that piglit won't like it much due to: a) The util functions use magic float mul conversion but when run inside softpipe/llvmpipe, denorms are flushed to zero, therefore when the conversion is from/to f16 denorm the result will be zero. This is a bug which should be fixed in these functions (should not rely on denorms being available), but will happen elsewhere just the same (e.g. conversion to f16 render targets). b) The util functions use trunc round mode rather than round-to-nearest. This is NOT a bug (as it is a d3d10 requirement). This will result of rounding not representable finite values to MAX_F16 rather than INFINITY. My belief is the piglit tests are wrong here but it's difficult to tell (generally glsl rounding mode is undefined, however I'm not sure if rounding mode might need to be consistent for different operations). Nevertheless, for gl it would be better to use round-to-nearest, but using different rounding for GL and d3d10 is an unsolved problem (as it affects things like conversion to f16 render targets, clear colors, this shader opcode). Hence for now don't enable the cap bit (so the code is unused). (Code is from imirkin, comment from sroland) Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: drop scissor planes early if the tri is fully inside themRoland Scheidegger2016-02-022-69/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | If the tri is fully inside a scissor edge (or rather, we just use the bounding box of the tri for the comparison), then we can drop these additional scissor "planes" early. We do not even need to allocate space for them in the tri. The math actually appears to be slightly iffy due to bounding boxes being rounded, but it doesn't matter in the end. Those scissor rects are costly - the 4 planes from the scissor are already more expensive to calculate than the 3 planes from the tri itself, and it also prevents us from using the specialized raster code for small tris. This helps openarena performance by about 8% or so. Of course, it helps there that while openarena often enables scissoring (and even moves the scissor rect around) I have not seen a single tri actually hit the scissor rect, ever. v2: drop individual scissor edges, and do it earlier, not even allocating space for them. v3: help the compiler a bit with simpler code, suggested by Brian. Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: minor cleanup of sse2 for calc_fixed_positionRoland Scheidegger2016-02-021-6/+5
| | | | | | Just slightly simpler assembly. Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: use vector loads for (optimized) tri raster funcsRoland Scheidegger2016-02-022-37/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we switched to 64bit rasterization, we could no longer use straight aligned loads for loading the plane data. However, what the code actually does for loading 3 planes, is 12 scalar loads + 9 unpacks, and then there's another 8 unpacks for the transpose we need (!). It would be possible to do the (scalar) loads of course already transposed (at least saving the additional unpacks), however instead just use (un)aligned vector loads, and recalculate the eo values, which is much less instructions (note in case of the triangle_32_3_4 case, the eo values are not even used, making the scalar loads + unpacks for them all the more pointless). This drops execution time of the triangle_32_3_4 function considerably, albeit it doesn't really make a measurable difference (for small tris we're essentially limited by vertex throughput in any case), for triangle_32_3_16 it's essentially noise (the loop is more costly than the initial code there). (I'm thinking about just ditching storing the eo values in the plane data, so could switch back to using aligned planes, however right now they are still used in the other raster functions dealing with planes with scalar code. Also not touching the ppc code, might not be that bad there in any case.) Reviewed-by: Brian Paul <[email protected]>
* i965: Provide sse2 version for rgba8 <-> bgra8 swizzleRoland Scheidegger2016-02-022-12/+62
| | | | | | | | | | | | | The existing code used ssse3, and because it isn't compiled in a separate file compiled with that, it is usually not used (that, of course, could be fixed...), whereas sse2 is always present at least with 64bit builds. This should be pretty much as fast as the pshufb version, albeit those code paths aren't really used on chips without llc in any case. v2: fix andnot argument order, add comments v3: use pshuflw/hw instead of shifts (suggested by Matt Turner), cut comments Reviewed-by: Matt Turner <[email protected]>
* mesa: fix typo in python scriptsRoland Scheidegger2016-02-022-2/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* virgl: also build vtest for AndroidRob Herring2016-02-023-2/+35
| | | | | | | Enabling swrast on Android causes a link error because vtest is missing. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* virgl: fix reference counting of prime handlesRob Herring2016-02-022-12/+33
| | | | | | | | | | The virgl reference counting of buffers is broken for prime fd buffers. Each prime fd passed into virgl_drm_winsys_resource_create_handle creates a new resource. The solution requires creating a separate hash table to track flink names separately from prime handles. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* virgl: reuse screen when fd is already openRob Herring2016-02-025-8/+97
| | | | | | | | | | It is necessary to share the screen between mesa and gralloc to properly ref count resources. This implements a hash lookup on the file description to re-use an already created screen. This is a similar implementation as freedreno and radeon. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nouveau/video: wrap assertion within #ifndef NDEBUGMauro Rossi2016-02-011-0/+2
| | | | | | | | | | | | The change is necessary to avoid the following building error in android: external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c: In function 'nouveau_vp3_bsp_next': external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c:269:14: error: 'bsp_bo' undeclared (first use in this function) assert(bsp_bo->size >= str_bsp->w0[0] + num_bytes[i]); ^ This matches the declaration of the variables in question. Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: treat a write as a read for range purposesIlia Mirkin2016-02-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use this logic to detect live ranges and then do plain renaming across the whole codebase. As such, to prevent WaW hazards, we have to treat a write as if it were also a read. For example, the following sequence was observed before this patch: 13: UIF TEMP[6].xxxx :0 14: ADD TEMP[6].x, CONST[6].xxxx, -IN[3].yyyy 15: RCP TEMP[7].x, TEMP[3].xxxx 16: MUL TEMP[3].x, TEMP[6].xxxx, TEMP[7].xxxx 17: ADD TEMP[6].x, CONST[7].xxxx, -IN[3].yyyy 18: RCP TEMP[7].x, TEMP[3].xxxx 19: MUL TEMP[4].x, TEMP[6].xxxx, TEMP[7].xxxx While after this patch it becomes: 13: UIF TEMP[7].xxxx :0 14: ADD TEMP[7].x, CONST[6].xxxx, -IN[3].yyyy 15: RCP TEMP[8].x, TEMP[3].xxxx 16: MUL TEMP[4].x, TEMP[7].xxxx, TEMP[8].xxxx 17: ADD TEMP[7].x, CONST[7].xxxx, -IN[3].yyyy 18: RCP TEMP[8].x, TEMP[3].xxxx 19: MUL TEMP[5].x, TEMP[7].xxxx, TEMP[8].xxxx Most importantly note that in the first example, the second RCP is done on the result of the MUL while in the second, the second RCP should have the same value as the first. Looking at the GLSL source, it is apparent that both of the RCP's should have had the same source. Looking at what's going on, the GLSL looks something like float tmin_8; float tmin_10; tmin_10 = tmin_8; ... lots of code ... tmin_8 = tmpvar_17; ... more code that never looks at tmin_8 ... And so we end up with a last_read somewhere at the beginning, and a first_write somewhere at the bottom. For some reason DCE doesn't remove it, but even if that were fixed, DCE doesn't handle 100% of cases, esp including loops. With the last_read somewhere high up, we overwrite the previously correct (and large) last_read with a low one, and then proceed to decide to merge all kinds of junk onto this temp. Even if that weren't the case, and there were just some writes after the last read, then we might still overwrite a merged value with one of those. As a result, we should treat a write as a last_read for the purpose of determining the live range. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Cc: [email protected]
* i965/gen7+: Use NIR for lowering of pack/unpack opcodes.Matt Turner2016-02-013-19/+29
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Implement nir_op_pack_uvec2_to_uint.Matt Turner2016-02-011-0/+18
| | | | | | | And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced by lowering pack[SU]norm4x8 which the vec4 backend does not need. Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add lowering support for unpacking opcodes.Matt Turner2016-02-012-0/+32
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add lowering support for packing opcodes.Matt Turner2016-02-014-0/+66
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Implement support for extract_word.Matt Turner2016-02-015-0/+56
| | | | | | The vec4 backend will lower it. Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add opcodes to extract bytes or words.Matt Turner2016-02-013-0/+28
| | | | | | The uint versions zero extend while the int versions sign extend. Reviewed-by: Iago Toral Quiroga <[email protected]>
* glsl: Remove 2x16 half-precision pack/unpack opcodes.Matt Turner2016-02-019-170/+8
| | | | | | i965/fs was the only consumer, and we're now doing the lowering in NIR. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.Matt Turner2016-02-013-11/+7
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add lowering of nir_op_unpack_half_2x16.Matt Turner2016-02-012-4/+29
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Make separate nir_options for scalar/vector stages.Matt Turner2016-02-011-28/+33
| | | | | | | We'll want to have different lowering options set for scalar/vector stages. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Move brw_compiler_create() to new brw_compiler.c.Matt Turner2016-02-015-133/+161
| | | | | | | A future patch will want to use designated initalizers, which aren't available in C++, but this is C. Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Make argument order of unop_convert match binop_convert.Matt Turner2016-02-011-10/+10
| | | | | | Strangely the return and parameter types were reversed. Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: enable enums for OES_geometry_shaderMarta Lofstedt2016-02-012-36/+98
| | | | | | | | | | | | | Enable GL_OES_geometry_shader enums for OpenGL ES 3.1. V4: EXTRA tokens updated according to comments from Ilia Mirkin. V5: Account for check_extra does not evaluate "or" lazy. Fix issues with EXTRA_EXT_FB_NO_ATTACH_CS. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: Add DragonFly supportFrançois Tigeot2016-01-311-1/+1
| | | | | Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* nv50/ir: get rid of memory stores with nop valuesIlia Mirkin2016-01-301-0/+6
| | | | | | | | | | | | | | | | | | | | This happens especially with exports and varying packing, where the last bits aren't always filled in. We end up trying to do quad-wide stores, which ends up being a lot of register moves that carefully preserve the nop value. Instead don't do the stores. total instructions in shared programs : 6131375 -> 6125267 (-0.10%) total gprs used in shared programs : 910139 -> 895501 (-1.61%) total local used in shared programs : 15328 -> 15328 (0.00%) local gpr inst helped 0 7442 4693 hurt 0 90 2687 Most of the helped/hurt instruction changes are by one or two ops because can no longer do quad-wide stores in all cases. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix false global CSE on instructions with multiple defsIlia Mirkin2016-01-301-0/+2
| | | | | | | | | | | | | | | | | | | | | If an instruction has multiple defs, we have to do a lot more checks to make sure that we can move it forward. Among other things, various code likes to do a, b = tex() if () c = a else c = b which means that a single phi node will have results pointing at the same instruction. We obviously can't propagate the tex in this case, but properly accounting for this situation is tricky. Just don't try for instructions with multiple defs. This fixes about 20 shaders in shader-db, including the dolphin efb2ram shader. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50,nvc0: fix buffer clearing to respect engine alignment requirementsIlia Mirkin2016-01-302-52/+247
| | | | | | | | | | | | | | | It appears that the nvidia render engine is quite picky when it comes to linear surfaces. It doesn't like non-256-byte aligned offsets, and apparently doesn't even do non-256-byte strides. This makes arb_clear_buffer_object-unaligned pass on both nv50 and nvc0. As a side-effect this also allows RGB32 clears to work via GPU data upload instead of synchronizing the buffer to the CPU (nvc0 only). Signed-off-by: Ilia Mirkin <[email protected]> # tested on GF108, GT215 Tested-by: Nick Sarnie <[email protected]> # GK208 Cc: [email protected]
* freedreno/ir3: ignore clip-vertex varyingRob Clark2016-01-301-1/+4
| | | | | | | | | | | Since we emulate clip-planes, the clip-vertex is used within the VS itself (thanks to nir_lower_clip). So just ignore it as a VS output. Fixes a boatload of piglit tests that were asserting on unknown varying slot. (Also unrelated spelling/typo fix.) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't ignore local varsRob Clark2016-01-301-1/+7
| | | | | | | | | | | With glsl_to_nir we end up with local variables, instead of global, for arrays. Note that we'll eventually have to do something more clever, I think, when we support multiple functions, but that will probably take some work in a few places. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle tex instrs w/ const offsetRob Clark2016-01-301-0/+16
| | | | | | Something we start to see with glsl_to_nir. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: support load_front_face intrinsicRob Clark2016-01-301-2/+14
| | | | | | | With tgsi_to_nir we get this as a normal input with VARYING_SLOT_FACE. But glsl_to_nir plus nir_lower_system_values this becomes an intrinsic. Signed-off-by: Rob Clark <[email protected]>
* freedreno: limit string marker to max packet sizeRob Clark2016-01-301-0/+3
| | | | | | Experimentally derived max size. Signed-off-by: Rob Clark <[email protected]>
* nvc0: avoid crashing when there are holes in vertex array bindingsIlia Mirkin2016-01-291-3/+13
| | | | | | | | | When using the "shared" vertex array configuration strategy, we bind each of the buffers as a separate array. However there can be holes in such vertex buffer lists, so just emit a disable for those. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0: enable atomic counters and ssboIlia Mirkin2016-01-294-4/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: handle new TGSI MEMBAR opcodeIlia Mirkin2016-01-291-0/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix atomic compare-and-swap argumentsIlia Mirkin2016-01-293-5/+8
| | | | | | | Teach the emitter that the two registers are sequential, and drop the second arg entirely, in favor of a double-wide first argument. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for indirect buffer loadingIlia Mirkin2016-01-292-10/+31
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add SUQ op by reading the info from driver constbufIlia Mirkin2016-01-296-3/+21
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for BUFFER accessesIlia Mirkin2016-01-296-11/+147
| | | | | | | This largely leaves the existing image logic alone. When image support is added this will have to be harmonized somehow. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: handle shader buffer memory barrierIlia Mirkin2016-01-291-0/+4
| | | | | | | Issue a MEM_BARRIER. No idea if this is sufficient. As there are no tests for this, it'll have to do for now. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add state management for shader buffersIlia Mirkin2016-01-295-8/+111
| | | | | | | (address, length) pairs are uploaded to the driver constbuf as well to make these values available to the shaders. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: double per-shader stage driver constants areaIlia Mirkin2016-01-293-15/+15
| | | | | | We need to store a lot more info now with per-buffer address/size. Signed-off-by: Ilia Mirkin <[email protected]>
* trace: add support for set_shader_buffersIlia Mirkin2016-01-293-0/+60
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) v1 -> v2: add arg_begin/arg_end around buffer array Reviewed-by: Samuel Pitoiset <[email protected]>
* st/mesa: enable ARB_shader_storage_buffer_object when supportedIlia Mirkin2016-01-291-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: add shader buffer barrier bitIlia Mirkin2016-01-292-0/+5
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: add support for memory barrier intrinsicsIlia Mirkin2016-01-291-0/+45
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v2) v1 -> v2: use TGSI_MEMBAR defines
* st/mesa: use RESQ to find buffer sizeIlia Mirkin2016-01-291-4/+18
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
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