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* radv: add radv_emit_shader_pointer() helperSamuel Pitoiset2018-05-173-13/+18
* radv: add some helpers for cleaning up radv_get_preamble_cs()Samuel Pitoiset2018-05-171-86/+128
* amd: remove support for LLVM 4.0Marek Olšák2018-05-1713-229/+121
* docs: update calendar, add news and link release notes to 18.0.4Juan A. Suarez Romero2018-05-173-7/+8
* docs: add sha256 checksums for 18.0.4Juan A. Suarez Romero2018-05-171-1/+2
* docs: add release notes for 18.0.4Juan A. Suarez Romero2018-05-171-0/+156
* mesa: The glArrayElement api is independent of the current program.Mathias Fröhlich2018-05-172-2/+2
* mesa: Flag _NEW_ARRAY only if we are changing ctx->Array.VAO.Mathias Fröhlich2018-05-171-6/+14
* mesa: Remove flush_vertices argument from VAO methods.Mathias Fröhlich2018-05-179-57/+51
* mesa: Remove FLUSH_VERTICES from VAO state changes.Mathias Fröhlich2018-05-171-59/+6
* docs: add 18.0.5 in the release calendarJuan A. Suarez Romero2018-05-171-1/+8
* swr/rast: Added FEClipRectangles eventAlok Hota2018-05-172-0/+4
* swr/rast: Whitespace and tab-to-spaces changesAlok Hota2018-05-175-17/+18
* swr/rast: fix VCVTPD2PS generation for AVX512Alok Hota2018-05-171-2/+10
* swr/rast: Rectlist support for GSAlok Hota2018-05-176-1/+102
* swr/rast: Remove unneeded virtual from methodsAlok Hota2018-05-171-2/+2
* broadcom/vc4: Native fence fd supportStefan Schake2018-05-176-11/+107
* broadcom/vc4: Store job fence in syncobjStefan Schake2018-05-173-4/+35
* broadcom/vc4: Detect syncobj supportStefan Schake2018-05-172-0/+7
* broadcom/vc4: Bump libdrm requirementStefan Schake2018-05-172-0/+8
* drm-uapi: Update vc4 header with syncobj submit supportStefan Schake2018-05-171-3/+10
* broadcom/vc4: Drop libdrm_vc4 requirementStefan Schake2018-05-171-1/+0
* v3d: Add support for glSampleMask / glSampleCoverage.Eric Anholt2018-05-177-5/+36
* v3d: Enable NaN propagation in the VS and CS as well.Eric Anholt2018-05-174-4/+12
* i965/blorp: Disable BLORP clear color updatesNanley Chery2018-05-171-2/+4
* intel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flagNanley Chery2018-05-172-2/+9
* i965/blorp: Also skip the fast clear if the clear color differsNanley Chery2018-05-171-4/+3
* i965/clear: Drop a stale comment in fast_clear_depthNanley Chery2018-05-171-4/+0
* i965: Update the indirect buffer in set_clear_colorNanley Chery2018-05-172-37/+13
* i965/clear: Remove an early return in fast_clear_depthNanley Chery2018-05-171-5/+0
* i965: Use set_clear_color for depth miptreesNanley Chery2018-05-173-19/+2
* Revert "i965: Make the miptree clear color setter take a gl_color_union"Nanley Chery2018-05-173-7/+6
* i965/miptree: Unify aux buffer allocationNanley Chery2018-05-172-142/+82
* i965: Prepare to delete intel_miptree_alloc_ccs()Nanley Chery2018-05-173-15/+16
* i965/miptree: Drop the mt param from alloc_aux_bufferNanley Chery2018-05-171-5/+4
* i965/miptree: Drop the alloc_flags param from alloc_aux_bufferNanley Chery2018-05-171-15/+14
* i965/miptree: Drop the name param from alloc_aux_bufferNanley Chery2018-05-171-5/+4
* i965/miptree: Initialize the indirect clear color to zeroNanley Chery2018-05-171-11/+22
* i965/miptree: Add and use a memset option in alloc_aux_bufferNanley Chery2018-05-171-37/+31
* i965/miptree: Zero-initialize CCS_D buffersNanley Chery2018-05-171-6/+4
* i965/miptree: Fix handling of uninitialized MCS buffersNanley Chery2018-05-171-7/+7
* radv: only declare the ESGS rings for pre GFX9 chipsSamuel Pitoiset2018-05-171-4/+10
* radv: allow to print GPU info with RADV_DEBUG=infoSamuel Pitoiset2018-05-172-0/+5
* radv: do not emit unnecessary ES output storesSamuel Pitoiset2018-05-171-3/+23
* radv: do not emit unnecessary GS output storesSamuel Pitoiset2018-05-171-0/+7
* radv: only pass the global BO list at submit time if enabledSamuel Pitoiset2018-05-171-2/+6
* radv: remove the radv_finishme() when compiling shadersSamuel Pitoiset2018-05-171-4/+0
* radv: remove radv_device::llvm_supports_spillSamuel Pitoiset2018-05-173-7/+1
* mesa: add glUniform*ui{v} support to display listsTimothy Arceri2018-05-171-33/+17
* radeonsi: create .gitignoreDieter Nützel2018-05-161-0/+2
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