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* mesa: fix debug/error messages in glColorMaski()Samuel Pitoiset2017-08-241-4/+4
| | | | | | | Trivial. While we are at it, adjust indentation. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: stop adding pointers from bindless structs to the cacheTimothy Arceri2017-08-241-4/+8
| | | | | | | This is so we always create reproducible cache entries. Consistency is required for verification of any third party distributed shaders. Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: stop adding pointers from shader_info to the cacheTimothy Arceri2017-08-241-6/+25
| | | | | | | This is so we always create reproducible cache entries. Consistency is required for verification of any third party distributed shaders. Reviewed-by: Samuel Pitoiset <[email protected]>
* compiler: move pointers to the start of shader_infoTimothy Arceri2017-08-241-3/+3
| | | | | | | This will allow us to easily skip them when writting the struct to disk cache. Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: always write a name/label string to the cacheTimothy Arceri2017-08-241-4/+7
| | | | | | | | | In the following patch we will stop writing the pointer to cache. Unfortunately adding empty strings to that cache seems to be the only thing we can do here once we no longer have the pointers. Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: don't write uniform storage offset if there isn't oneTimothy Arceri2017-08-241-3/+10
| | | | | | | This is so we always create reproducible cache entries. Consistency is required for verification of any third party distributed shaders. Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: add has_uniform_storage() helper to shader cacheTimothy Arceri2017-08-241-6/+13
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: stop adding pointers from glsl_struct_field to the cacheTimothy Arceri2017-08-241-7/+38
| | | | | | | This is so we always create reproducible cache entries. Consistency is required for verification of any third party distributed shaders. Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: stop adding pointers from gl_shader_variable to the cacheTimothy Arceri2017-08-241-12/+28
| | | | | | | This is so we always create reproducible cache entries. Consistency is required for verification of any third party distributed shaders. Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: allow NULL to be passed to encode_type_to_blob()Timothy Arceri2017-08-241-0/+10
| | | | | | This will be used by the following commit. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx9: don't expose linear depth on vega.Dave Airlie2017-08-241-0/+4
| | | | | | | | This just zeros out the linear flags for gfx9 + depth formats. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: don't degrade tiling mode for small compressed or depth texture.Dave Airlie2017-08-241-6/+10
| | | | | | | | | This is what radeonsi does, so we should do the same, also vega doesn't support linear depth textures anyways. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: only minify image view width/height/depth before gfx9.Dave Airlie2017-08-242-7/+15
| | | | | | | | | | | For gfx9 the addressing for images has changed, so we need to provide the hw with the level0, however we still need to scale for format block differences (so our compressed upload paths still work). Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/image: don't rescale width/height if the format isn't changingDave Airlie2017-08-241-4/+6
| | | | | | | | | If the image view has the same format, we don't need to rescale the w/h. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: cleanup some image view descriptor setup.Dave Airlie2017-08-242-13/+21
| | | | | | | | | | | | Avoid passing the vulkan image creation into the image view descriptor setup. This cleans up the usage of range inside the init, instead using the properly inited values in the image view. This is just a cleanup but some future vega changes will depend on it. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: emit sx_mrt_blend registersDave Airlie2017-08-243-3/+134
| | | | | | | | | | | | | GFX9 needs the SX MRT blend registers programmed, port over the code from radeonsi to workout the values from the blend state, and program the registers on rbplus systems. This fixes lots of: dEQP-VK.pipeline.blend.* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: bump space check for indexed draw.Dave Airlie2017-08-241-1/+1
| | | | | | | | | | | For the GFX9 packet we need one more dword. Fixes an assert in: dEQP-VK.draw.shader_draw_parameters.base_vertex.draw_indexed Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fixup db/stencil disable.Dave Airlie2017-08-241-3/+7
| | | | | | | | This fixes disabled Z/stencil. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix level count in color register setup.Dave Airlie2017-08-241-1/+1
| | | | | | | | There was an off by one here. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: use total levels in texture descriptorDave Airlie2017-08-241-1/+1
| | | | | | | | | We need to use all the levels when filling out the gfx9 descriptor. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Implement bc optimize.Bas Nieuwenhuizen2017-08-243-0/+33
| | | | | | | | Seems like we actually enabled it already, but did not implement the shader part. With this patch we do. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: refactor input variable iteration.Bas Nieuwenhuizen2017-08-241-19/+11
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* i965: Stop using wm_prog_data->binding_table.render_target_start.Kenneth Graunke2017-08-232-9/+10
| | | | | | | | | | | | | Render target surfaces always start at binding table index 0. This is required for us to use headerless FB writes, which we really want to do. So, we'll never change that. Given that, it's not necessary to look up a wm_prog_data field which we already know contains 0. We can drop the dependency in brw_renderbuffer_surfaces (Gen4-5)...which was already confusingly missing from gen6_renderbuffer_surfaces. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add a brw_wm_prog_data::has_render_target_reads field.Kenneth Graunke2017-08-233-4/+5
| | | | | | | State upload code should use prog_data rather than poking at shader_info directly. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Inline brw_update_renderbuffer_surfaces().Kenneth Graunke2017-08-232-38/+20
| | | | | | Less baklava layers. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Pass fb into emit_null_surface instead of dimensions.Kenneth Graunke2017-08-231-16/+12
| | | | | | | We either want the framebuffer dimensions or 1x1x1. Passing fb and falling back to 1x1x1 lets us shorten some calls. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Devirtualize update_renderbuffer_surface.Kenneth Graunke2017-08-234-30/+5
| | | | | | Replace piles of my own boilerplate with 1-2 lines of code. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Delete update_renderbuffer_surface flags.Kenneth Graunke2017-08-232-21/+5
| | | | | | | | | We don't need yet another set of flags. The function already has access to both brw and the unit, so it can check brw->draw_aux_buffer_disabled itself in one line of code. The layered flag was only used to assert that Gen4-5 doesn't do layered rendering, which isn't that useful. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Make brw_update_renderbuffer_surface static.Kenneth Graunke2017-08-232-11/+6
| | | | | | | | Also rename it to gen6_update_renderbuffer_surface, as this is the function for Gen6+. Having functions named "brw_*" and "gen4_*" is confusing...if we're using gens, let's stick with those. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Drop BRW_NEW_BLORP from SURFACE_STATE setup code.Kenneth Graunke2017-08-235-29/+1
| | | | | | | BLORP invalidates the binding tables, but it doesn't destroy any of the existing SURFACE_STATE entries in the statebuffer. We can reuse those. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit.Kenneth Graunke2017-08-238-5/+25
| | | | | | | | | | | | | | | | | | | When changing fast clear colors, we need to emit new SURFACE_STATE with the updated color at the next draw call. Most things work today because the atoms that handle SURFACE_STATE for images (mutable images, textures, render targets) also listen to BRW_NEW_BLORP, causing us to re-emit these on every BLORP operation. However, this is overkill - most BLORP operations don't require us to re-emit SURFACE_STATE. One case where this is broken today is a fast clear to a different color followed by a non-coherent framebuffer fetch. The renderbuffer read atom doesn't listen to BRW_NEW_BLORP, and would not get the new fast clear color. Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop Gen7+ nonsense from brw_ff_gs.c.Kenneth Graunke2017-08-231-4/+3
| | | | | | | | | | brw_ff_gs.c is about using the geometry shader to implement things that the fixed function ought to do, but doesn't on old hardware. Gen7+ does not need this. We should drop the misleading comment about Gen7 not using geometry shaders. Reviewed-by: Timothy Arceri <[email protected]>
* i965: Only set key->flat_shade if COL0/COL1 are written.Kenneth Graunke2017-08-231-1/+3
| | | | | | This may reduce some recompiles. Reviewed-by: Timothy Arceri <[email protected]>
* i965: Clean up brwNewProgram().Kenneth Graunke2017-08-231-28/+5
| | | | | | | | | | All shader stages do the exact same thing, so we don't need the switch statement, or the redundant FS case. I believe these used to be different before Tim eliminated the (e.g.) brw_vertex_program subclasses. Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* st/va: exclude the buffer reallocation for encode caseLeo Liu2017-08-231-1/+1
| | | | | | | | | Since encoder only support de-interlaced buffers. v2: move to parameter call to tell dec/enc Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* swr: limit pipe_draw_info->restart_index usageTim Rowley2017-08-231-1/+4
| | | | | | | | Only copy this value when in restart drawing mode. Eliminates valgrind errors when running trivial programs. Reviewed-by: Bruce Cherniak <[email protected]>
* radeonsi: fix wrong assertion in si_init_bindless_descriptors()Samuel Pitoiset2017-08-231-1/+1
| | | | | | Bad mistake, sorry. Signed-off-by: Samuel Pitoiset <[email protected]>
* radeon/video: Return false explicitly for HEVC if not the caseLeo Liu2017-08-231-0/+1
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: Fix the math formula of U2I64Gwan-gyeong Mun2017-08-231-2/+2
| | | | | | | | | | | | | before: dst.xy = (uint64_t) src0.x dst.zw = (uint64_t) src0.y after: dst.xy = (int64_t) src0.x dst.zw = (int64_t) src0.y Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: Add missing word "Not"Gwan-gyeong Mun2017-08-231-1/+1
| | | | | Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi: store opcode mnemonics in a separate tableNicolai Hähnle2017-08-232-6/+16
| | | | | | | | | | They are only used for debug info. Together with making tgsi_opcode_info::opcode a bitfield, this reduces the size of tgsi_opcode_info on 64-bit systems from 24 bytes to 4 bytes, and makes the whole data structure a bit more linker friendly. Reviewed-by: Marek Olšák <[email protected]>
* gallium: use tgsi_get_opcode_name instead of tgsi_opcode_info::mnemonicNicolai Hähnle2017-08-235-7/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* tgsi: macro-ify the opcodes tableNicolai Hähnle2017-08-233-251/+263
| | | | | | | | | So we can easily re-arrange members of tgsi_opcode_info, and readers of the code don't have to guess what all the 0s mean. Mostly done with regex search&replace. Reviewed-by: Marek Olšák <[email protected]>
* tgsi: remove post_indent from some 64-bit opcodesNicolai Hähnle2017-08-231-6/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* tgsi: reduce tgsi_opcode_info::pre_dedent and post_indent to 1 bitNicolai Hähnle2017-08-231-2/+2
| | | | | | | | It's not clear why they were ever 2 bits to begin with. Perhaps the original intent was to use signed values, but that doesn't seem to have ever been the case in master. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: fix saving multi-part command streamsNicolai Hähnle2017-08-231-1/+1
| | | | | | Use the correct type to fix pointer arithmetic. Reviewed-by: Marek Olšák <[email protected]>
* ac/debug: invoke valgrind checks while parsing IBsNicolai Hähnle2017-08-231-0/+20
| | | | | | Help catch garbage data written into IBs. Reviewed-by: Marek Olšák <[email protected]>
* ac/debug: annotate IB dumps with the raw valuesNicolai Hähnle2017-08-231-18/+66
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/debug: use an explicit getter for fetching words from the IBNicolai Hähnle2017-08-231-153/+215
| | | | | | Guard against out-of-bounds accesses, and prepare for upcoming changes. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: update comment describing indices into sctx->descriptorsNicolai Hähnle2017-08-231-6/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
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