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* intel/fs: Add an UNDEF instruction to avoid excess live rangesJason Ekstrand2019-06-046-5/+35
* spirv: Update the OpenCL.std.h headerCaio Marcelo de Oliveira Filho2019-06-042-144/+339
* radv: Use bo metadata for imported image tiling on Android.Bas Nieuwenhuizen2019-06-043-14/+61
* vl: Enable DRM by default.Bas Nieuwenhuizen2019-06-043-4/+4
* anv: Advertise support for VK_EXT_fragment_shader_interlockJason Ekstrand2019-06-043-0/+12
* spirv: Implement SPV_EXT_fragment_shader_interlockJason Ekstrand2019-06-042-0/+38
* spirv: Update the headers from latest Khronos masterJason Ekstrand2019-06-042-3/+330
* vulkan: Update the XML and headers to 1.1.110Jason Ekstrand2019-06-042-23/+456
* ac/nir: mark some texture intrinsics as convergentRhys Perry2019-06-041-0/+18
* radv: fix some compiler warningsRhys Perry2019-06-041-4/+4
* intel/fs: Skip registers faster when setting spill costsJason Ekstrand2019-06-041-2/+10
* radeonsi/nir: Fix type in bindless address computationConnor Abbott2019-06-041-2/+2
* etnaviv: implement set_active_query_state(..) for hw queriesChristian Gmeiner2019-06-041-1/+10
* radv: do not use gfx fast depth clears for layered depth/stencil imagesSamuel Pitoiset2019-06-041-0/+1
* ac,radv: do not emit vec3 for raw load/store on SISamuel Pitoiset2019-06-044-8/+20
* intel/compiler: Fix assertions in brw_alu3Sagar Ghuge2019-06-031-3/+3
* iris: Fix SO stride units for DrawTransformFeedbackKenneth Graunke2019-06-032-2/+2
* st/glsl: make sure to propagate initialisers to driver storageTimothy Arceri2019-06-045-27/+23
* spirv: Like Uniform, do nothing for UniformIdCaio Marcelo de Oliveira Filho2019-06-032-0/+3
* spirv: Implement SpvOpCopyLogicalCaio Marcelo de Oliveira Filho2019-06-031-0/+2
* spirv: Generalize OpSelectCaio Marcelo de Oliveira Filho2019-06-031-38/+48
* spirv: Move OpSelect handling to a functionCaio Marcelo de Oliveira Filho2019-06-031-60/+66
* nir/vars_to_ssa: Handle UNDEF_NODE in more placesCaio Marcelo de Oliveira Filho2019-06-031-4/+8
* ac/registers: don't use the si, cik, vi names, use gfxNMarek Olšák2019-06-036-1405/+1405
* amd/common: use generated register headerNicolai Hähnle2019-06-0326-16362/+26
* amd/common: use SH{0,1}_CU_EN definitions only of COMPUTE_STATIC_THREAD_MGMT_SE0Nicolai Hähnle2019-06-032-10/+10
* amd/common: unify PITCH_GFX6 and PITCH_GFX9Nicolai Hähnle2019-06-035-20/+20
* amd/common: rename R_3F2_CONTROL to IB_CONTROL for disambiguationNicolai Hähnle2019-06-032-2/+2
* amd/common: cleanup DATA_FORMAT/NUM_FORMAT field namesNicolai Hähnle2019-06-036-25/+25
* amd/common: derive ac_debug tables from register JSONNicolai Hähnle2019-06-034-177/+131
* amd/registers: add JSON description of packet3 fieldsNicolai Hähnle2019-06-031-0/+338
* amd/registers: add JSON descriptions of registersNicolai Hähnle2019-06-031-0/+15985
* amd/registers: scripts for processing register descriptions in JSONNicolai Hähnle2019-06-035-0/+1631
* freedreno: Fix GCC build error.Vinson Lee2019-06-031-1/+1
* mesa: Use string literals for format stringsMark Janes2019-06-031-3/+3
* iris: Always reserve binding table space for NIR constantsCaio Marcelo de Oliveira Filho2019-06-032-9/+14
* iris: Print binding tables when INTEL_DEBUG=btCaio Marcelo de Oliveira Filho2019-06-033-0/+55
* iris: Compact binding tablesCaio Marcelo de Oliveira Filho2019-06-033-76/+234
* iris: Create an enum for the surface groupsCaio Marcelo de Oliveira Filho2019-06-033-35/+45
* iris: Handle binding table in the driverCaio Marcelo de Oliveira Filho2019-06-036-121/+232
* iris: Pull brw_nir_analyze_ubo_ranges() call out setup_uniformsCaio Marcelo de Oliveira Filho2019-06-031-3/+10
* spirv: Implement OpPtrEqual, OpPtrNotEqual and OpPtrDiffCaio Marcelo de Oliveira Filho2019-06-031-0/+64
* nir: Add functions to subtract and compare addressesCaio Marcelo de Oliveira Filho2019-06-032-0/+54
* nir: Add nir_ball_iequal() helperCaio Marcelo de Oliveira Filho2019-06-031-0/+13
* mesa: ARB program parser should clean parametersSergii Romantsov2019-06-032-2/+13
* freedreno/ir3: fix counting and printing for half registers.Hyunjun Ko2019-06-034-9/+20
* freedreno/ir3: Fix up the half reg source even when src instr==NULLNeil Roberts2019-06-031-3/+2
* freedreno/ir3: Add a 16-bit implementation of nir_op_imulNeil Roberts2019-06-031-9/+15
* freedreno/ir3: set dst type of alu instructions correctly.Hyunjun Ko2019-06-031-5/+8
* freedreno/ir3: adjust the bitsize of regs when an array loading.Hyunjun Ko2019-06-032-7/+16
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