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* panfrost/midgard: Add f2f64 supportBoris Brezillon2020-01-221-2/+4
| | | | | | | | So we can convert floats into doubles. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
* panfrost/midgard: Factorize f2f and u2u handlingBoris Brezillon2020-01-221-20/+7
| | | | | | | | | | Those size conversion operations work the same way apart from f2f using an fmov op code and u2u using an imov. Let's handle them in the same case block to avoid code duplication. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
* panfrost/midgard: Make sure promote_fmov() only promotes 32-bit imovsBoris Brezillon2020-01-221-0/+1
| | | | | | | | | mir_constant_float() assumes we're dealing with 32-bit integers/floats, which is only the case if reg_mode is equal to midgard_reg_mode_32. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
* panfrost/midgard: Rework mir_adjust_constants() to make it type/size agnosticBoris Brezillon2020-01-221-94/+69
| | | | | | | | | | Right now, constant combining is not supported in 16 bit mode, and 64 bit mode is simply ignored. Let's rework the function to make it type/bit-size agnostic. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
* panfrost/midgard: Use a union to manipulate embedded constantsBoris Brezillon2020-01-228-49/+85
| | | | | | | | | | | | Each instruction bundle can contain up to 16 constant bytes. The meaning of those byte is instruction dependent: it depends on the instruction native type (int, uint or float) and the instruction reg_mode (8, 16, 32 or 64 bit). Those different layouts can be exposed as a union to facilitate constants manipulation. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
* anv: ensure prog params are initialized with 0sLionel Landwerlin2020-01-221-1/+1
| | | | | | | | | | | | | | | | | | As a result of 9baa33cef01f our backend compiler leaves params pretty much untouched. So in order to avoid storing uninitialized values in the shader cache blobs, just 0 out this array. I've considered not even allocating this array which works on gen8+ but the vec4 backend still makes a copy of this array and so it crashes on memcpy on HSW. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 9baa33cef01f ("anv: Rework push constant handling") Reported-by: Tapani Pälli <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Tapani Pälli <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3516> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3516>
* panfrost: Fix crash in compute variant allocationAlyssa Rosenzweig2020-01-221-1/+2
| | | | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Fixes: d8a3501f1b2 ("panfrost: Dynamically allocate shader variants") Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3515> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3515>
* etnaviv: drm: Don't miscalculate timeoutGuido Günther2020-01-221-3/+2
| | | | | | | | | | The current code overflows (s * 1000000000) for s >= 5 but that is e.g. used in etna_bo_cpu_prep. Signed-off-by: Guido Günther <[email protected]> Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3509> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3509>
* egl: Fix _eglPointerIsDereferencable w/o mincore()Alexander van der Grinten2020-01-221-3/+4
| | | | | | | | | | | | | | | | On platforms without mincore(), _eglPointerIsDereferencable() currently just checks whether p != NULL. This is not sufficient: In the Wayland platform code (i.e., in get_wl_surface_proxy()), _eglPointerIsDereferencable() is called on the version field of `struct wl_egl_window` which is 3 on current versions of Wayland. This causes a segfault when trying to dereference p. Fix this behavior by assuming that the first page of the process is never dereferencable. Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3103> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3103>
* egl/android: fix buffer_count for applications setting max countTapani Pälli2020-01-221-6/+22
| | | | | | | | | | | | | Problem with previous solution was that it did not take account that some applications may set a max count for buffers. Therefore we need to query both min and max and clamp our setting based on that. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2373 Fixes: be08e6a4496 ("egl/android: Restrict minimum triple buffering for android color_buffers") Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3480> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3480>
* aco: Fix signedness compare warning.Timur Kristóf2020-01-221-1/+1
| | | | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>
* aco: Fix maybe-uninitialized warnings.Timur Kristóf2020-01-222-0/+4
| | | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>
* aco: Fix -Wstringop-overflow warnings in aco_span.Timur Kristóf2020-01-221-2/+2
| | | | | | | | | | | GCC does not understand how aco_span works. This patch fixes it by casting the aco_span's this pointer to uintptr_t rather than to a char pointer, effectively telling GCC not to try to figure it out. Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>
* radeon: Fix multiple definition error with radeon_debugTimur Kristóf2020-01-222-7/+17
| | | | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
* gallium: Fix a couple of multiple definition warnings.Timur Kristóf2020-01-221-4/+4
| | | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
* r600: Move get_pic_param to radeon_vce.cTimur Kristóf2020-01-222-4/+4
| | | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
* radeon: Move si_get_pic_param to radeon_vce.cTimur Kristóf2020-01-222-4/+4
| | | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
* intel/compiler: Fix array bounds warning on GCC 10.Timur Kristóf2020-01-221-0/+2
| | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* turnip: Add support for non-zero (still constant) UBO buffer indices.Eric Anholt2020-01-221-2/+3
| | | | | | | | | | | This was actually all ready to go at this point, and just needed to increment by the value. Fixes dEQP-VK.binding_model.shader_access.primary_cmd_buf.uniform_buffer.* Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3504> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3504>
* turnip: fix array/matrix varyingsJonathan Marek2020-01-211-2/+2
| | | | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>
* turnip: remove tu_sort_variables_by_locationJonathan Marek2020-01-211-48/+0
| | | | | | | | nir_assign_io_var_locations already does sorting. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>
* freedreno/ir3: allow inputs with the same locationJonathan Marek2020-01-211-9/+17
| | | | | | | | | turnip can have multiple inputs with the same location, and different location_frac. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>
* gitlab-ci: Skip ext_timer_query/time-elapsedMatt Turner2020-01-222-3/+3
| | | | | | | | | This test's result is unpredictable, so it may occasionally pass when we expect it to fail, thus causing the CI pipeline to fail. Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3498> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3498>
* intel/compiler: Test compaction on Gen <= 12Matt Turner2020-01-221-1/+1
| | | | | | | | With the previous commits we can now enable the unit test on Gen <= 12. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Validate fuzzed instructionsMatt Turner2020-01-223-1/+7
| | | | | | | ... before giving them to the instruction compactor. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Add unit tests for new EU validation checksMatt Turner2020-01-221-0/+396
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Validate some instruction word encodingsMatt Turner2020-01-221-10/+84
| | | | | | | | | | | Specifically, execution size, register file, and register type. I did not add validation for vertical stride and width because I don't believe it's possible to have an otherwise valid instruction with an invalid vertical stride or width, due to all of the other regioning restrictions. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Factor out brw_validate_instruction()Matt Turner2020-01-221-26/+35
| | | | | | | | | In order to fuzz test instructions, we first need to do some sanity checking first. Factoring out this function allows us an easy way to validate a single instruction. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Handle invalid compacted immediatesMatt Turner2020-01-221-1/+15
| | | | | | | | | | | 16-bit immediates need to be replicated through the 32-bit immediate field, so we should never see one that isn't. This does happen however in the fuzzer unit test, so returning false allows the fuzzer to reject this case. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Handle invalid inputs to brw_reg_type_to_*()Matt Turner2020-01-221-0/+6
| | | | | | | Necessary to handle these cases when we test fuzzed instructions. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Split hw_type tablesMatt Turner2020-01-221-23/+116
| | | | | | | | | | | | Previously we were sharing tables between generations that were nearly identical (i.e., Gen8 3-src adds HF support) and used a small bit of code to handle the differences. This is kind of a mess if you want to reject 64-bit types on platforms that don't support 64-bit types, so split the tables, allowing each generation's table to list exactly what it supports. Acked-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Add a INVALID_{,HW_}REG_TYPE macrosMatt Turner2020-01-223-5/+8
| | | | | | | | Since the enum brw_reg_type is packed, comparisons with -1 don't work directly, necessitating the cast. Add a macro to avoid this confusion. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Add NF some more placesMatt Turner2020-01-222-0/+5
| | | | | | | Necessary to handle these cases when we test fuzzed instructions. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Limit compaction unit tests to specific gensMatt Turner2020-01-221-9/+18
| | | | | | | | | Two of the tests emit instructions with MRF destinations, and MRFs aren't present on Gen7+. I think we were just lucky that this didn't cause a problem earlier since we were running the tests on Gen7-9. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Don't disassemble align1 3-src operands on Gen < 10Matt Turner2020-01-221-0/+12
| | | | | | | | | Since the platforms don't support align1 3-src instructions, the contents of these operands are not going to be meaningful. Just don't print them to avoid hitting some assertions in brw_inst functions. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Split has_64bit_types into float/intMatt Turner2020-01-228-27/+80
| | | | | | | Gen7 has 64-bit floats but not 64-bit ints. Acked-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Extract GEN_* macros into separate fileMatt Turner2020-01-222-37/+63
| | | | | | | Will be used by the instruction compaction unit test. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/compiler: Use ARRAY_SIZE()Matt Turner2020-01-221-22/+22
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
* intel/fs: Don't emit control barrier if only one thread is usedCaio Marcelo de Oliveira Filho2020-01-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When there's only one hardware thread (i.e. the dispatch width greater or equal to the workgroup size), there's no need to use a barrier to ensure all the invocations reach the same point in the shader, because they are already running lock-step. Results for SKL running Iris for shader-db tests with compute shaders total sends in shared programs: 18361 -> 18339 (-0.12%) sends in affected programs: 904 -> 882 (-2.43%) helped: 9 HURT: 0 helped stats (abs) min: 1 max: 5 x̄: 2.44 x̃: 2 helped stats (rel) min: 0.84% max: 21.43% x̄: 7.82% x̃: 2.67% 95% mean confidence interval for sends value: -3.31 -1.58 95% mean confidence interval for sends %-change: -14.67% -0.97% Sends are helped. Shaders from Aztec Ruins, Car Chase, Manhattan and DeusEx are helped. Results for ICL and TGL are similar to SKL. Results for BDW are similar to SKL except for DeusEx shader that has a workgroup size 16 but in BDW picks the SIMD8. Reviewed-by: Francisco Jerez <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
* intel/fs: Don't emit fence for shared memory if only one thread is usedCaio Marcelo de Oliveira Filho2020-01-211-13/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When there's only one hardware thread (i.e. the dispatch width greater or equal to the workgroup size), there's no need to synchronize shared memory access (SLM) since all the requests from a single thread are already synchronized. In such case, we just add a scheduling fence. To be able to identify that case for all platforms, move the handling of platforms prior to Gen11 (which don't have a separate SLM fence) after the optimization. Results for SKL running Iris for shader-db tests with compute shaders total sends in shared programs: 18395 -> 18361 (-0.18%) sends in affected programs: 938 -> 904 (-3.62%) helped: 9 HURT: 0 helped stats (abs) min: 1 max: 5 x̄: 3.78 x̃: 4 helped stats (rel) min: 1.56% max: 26.32% x̄: 10.33% x̃: 2.60% 95% mean confidence interval for sends value: -4.85 -2.71 95% mean confidence interval for sends %-change: -19.12% -1.54% Sends are helped. Shaders from Aztec Ruins, Car Chase, Manhattan and DeusEx are helped. Results for ICL and TGL are similar to SKL. Results for BDW are similar to SKL except for DeusEx shader that has a workgroup size 16 but in BDW picks the SIMD8. Reviewed-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
* intel/fs: Add workgroup_size() helperCaio Marcelo de Oliveira Filho2020-01-212-0/+10
| | | | | Reviewed-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
* intel/fs: Add FS_OPCODE_SCHEDULING_FENCECaio Marcelo de Oliveira Filho2020-01-213-0/+13
| | | | | | | | | | | | Like a SHADER_OPCODE_MEMORY_FENCE but doesn't doesn't generate any assembly code. Will be used when the compiler shouldn't reorder certain instructions but there's no need to generate code for the HW to do it -- as the ordering will be guaranteed by other means. Reviewed-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
* gallium: check all planes' pipe formats in case of multi-samplersDongwon Kim2020-01-211-5/+10
| | | | | | | | | | | | Current code only checks whether first plane's format is supported in case YUV format sampling is done by sampling each plane separately. It would be safer to check other planes' as well. Signed-off-by: Dongwon Kim <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2863> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2863>
* anv: Drop some workarounds that are no longer necessaryKenneth Graunke2020-01-211-61/+0
| | | | | | | | These workarounds are no longer required by 10th Gen hardware. Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495>
* iris: Drop some workarounds which are no longer necessaryKenneth Graunke2020-01-211-36/+1
| | | | | | | These workarounds are no longer required by 10th Gen hardware. Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495>
* turnip: Disable UBWC on images used as storage images.Eric Anholt2020-01-211-0/+12
| | | | | | | | | | | | | | The closed GL driver doesn't use UBWC on any storage images. It does tile mostly (skipping tiling on writeonly images, it seems), but for freedreno we've been enabling tiling in all cases and it's fine. We do need to disable UBWC, as tests fail otherwise and just plugging in the equivalent UBWC regs like we were setting up a texture isn't enough. Fixes dEQP-VK.image.atomic_operations.* Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
* turnip: Add limited support for storage images.Eric Anholt2020-01-216-19/+116
| | | | | | | | | | | So far this doesn't handle the texture state-based storage image access loads, and doesn't support descriptor arrays (same as SSBOs). The texture side is more tricky, since we have another remapping table to work around. This is enough to get some of dEQP-VK.image.atomic_operations.* working. Reviewed-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
* turnip: Refactor the intrinsic lowering.Eric Anholt2020-01-211-35/+48
| | | | | | | Too many things in one function, split them out based on the intrinsic. Reviewed-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
* turnip: Fix some whitespace around binary operators.Eric Anholt2020-01-211-3/+3
| | | | | | | Conforms to mesa style and the rest of turnip. Reviewed-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
* radeonsi: Drop PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS.Eric Anholt2020-01-211-1/+0
| | | | | | | | Now that we don't expose TGSI, we can stop exposing the flag. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 09:09:52 +0000