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* i965/gen8: Factor out texture surface state set-up from ↵Francisco Jerez2015-04-271-60/+77
| | | | | | | gen8_update_texture_surface(). This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function.
* i965/gen7: Factor out texture surface state set-up from ↵Francisco Jerez2015-04-272-54/+84
| | | | | | | gen7_update_texture_surface(). This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function.
* i965: Add helper functions to calculate the slice pitch of an array or 3D ↵Francisco Jerez2015-04-272-40/+84
| | | | miptree.
* scons: add target osmesa using gallium state tracker.Olivier Pena2015-04-277-1/+110
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* radeonsi: set an optimal value for DB_Z_INFO.ZRANGE_PRECISIONMarek Olšák2015-04-271-7/+2
| | | | | | Required because of a VI hw bug. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove deprecated and useless registersMarek Olšák2015-04-271-10/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove useless includesMarek Olšák2015-04-271-3/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: print winsys info with R600_DEBUG=infoMarek Olšák2015-04-272-0/+28
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* winsys/radeon: make radeon_bo_vtbl staticMarek Olšák2015-04-271-2/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* glsl: replace while loop with without_array functionTimothy Arceri2015-04-271-3/+1
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: support packing of arrays of arraysTimothy Arceri2015-04-271-8/+2
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: add arrays of arrays support to without_array functionTimothy Arceri2015-04-271-1/+6
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* docs/GL3: started adding support for shader_image_sizeMartin Peres2015-04-271-2/+2
| | | | Signed-off-by: Martin Peres <[email protected]>
* gallium/hud: add more options to customize HUD panesGediminas Jakutis2015-04-262-6/+161
| | | | | | | | | | | | | | | | Extends the syntax of GALLIUM_HUD environment variable to: - Add options to set the size and exact location of each pane. - Add an option to limit the maximum allowed value of the X axis on a pane, clamping the graph down to not go above this value. - Add an option to auto-adjust the value of the Y axis down to the highest value still visible on the graph. v2: - Make the patch simpler and smaller. - With dynamic auto-adjusting on, adjust the Y axis once per pane update instead of updating once every several seconds. - No longer mishandle pane height when having more than one graph per pane.
* i965: Fill out the rest of brw_debug_recompile_sampler_key().Kenneth Graunke2015-04-251-0/+8
| | | | | | | | | | This makes INTEL_DEBUG=perf report shader recompiles due to CMS vs. UMS/IMS differences and Sandybridge textureGather workarounds. Previously, we just flagged them as "Something else". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Disassemble sampler message names on Gen5+.Kenneth Graunke2015-04-251-4/+34
| | | | | | | | | | | | | | | | | | | | | | Previously, sampler messages were decoded as sampler (1, 0, 2, 2) mlen 6 rlen 8 { align1 1H }; I don't know how much time we've collectly wasted trying to read this format. I can never recall which number is the surface index, sampler index, message type, or...whatever that other number is. Figuring out the message name from the numerical code is also painful. Now they decode as: sampler sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; This is easy to read at a glance, and matches the format I used for render target formats. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Disallow constant propagation into POW on Gen 6.Matt Turner2015-04-251-2/+8
| | | | | Fixes assertion failures in three piglit tests on Gen 6 since commit 0087cf23e.
* mesa: add support for exposing up to GL4.2Ilia Mirkin2015-04-241-1/+45
| | | | | | | | | Add the 4.0/4.1/4.2 extensions lists to compute_version. A couple of extensions aren't in mesa yet, so those are marked with 0 until they become supported. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Add missing pixel_x/y to brw_instruction_name().Matt Turner2015-04-241-0/+5
| | | | Forgotten in commit 529064f6.
* i965/fs: Don't constant propagate into integer math instructions.Matt Turner2015-04-242-3/+5
| | | | | | Constant combining won't promote non-floats, so this isn't safe. Fixes regressions since commit 0087cf23e.
* docs: add news item and link release notes for mesa 10.5.4Emil Velikov2015-04-242-0/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: Add sha256 sums for the 10.5.4 releaseEmil Velikov2015-04-241-1/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit adb47b5b279b6fd920151aa7926af6ffd2069339)
* Add release notes for the 10.5.4 releaseEmil Velikov2015-04-241-0/+124
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit ea0d1f575c214c09ba3df12644a960e86e031766)
* mesa: put more info in glTexImage GL_OUT_OF_MEMORY error messageBrian Paul2015-04-241-1/+3
| | | | | | | Give the user some idea about the size of the texture which caused the GL_OUT_OF_MEMORY error. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Allow 2-src math instructions to have immediate src1.Matt Turner2015-04-242-7/+11
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Transform pow(x, 4) into (x*x)*(x*x).Matt Turner2015-04-241-0/+1
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* glsl: Transform pow(x, 4) into (x*x)*(x*x).Matt Turner2015-04-241-0/+20
| | | | | Reviewed-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix glGetActiveUniformsiv regressionTapani Pälli2015-04-241-4/+16
| | | | | | | | | | | Commit 7519ddb caused regression to glGetActiveUniformsiv. Patch adds back validation loop of all given uniforms before writing any values, not touching params in case of errors is tested by the conformance suite. Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90149 Reviewed-by: Martin Peres <[email protected]>
* mesa: refactor active attrib queries for glGetProgramivTapani Pälli2015-04-241-25/+14
| | | | | | | | | | | | | | | Main motivation here is to get rid of iterating IR and encapsulate queries within program resources. No functional changes. Piglit tests calling the modified functionality: - gl-get-active-attrib-returns-all-inputs - glsl-1.50-get-active-attrib-array - getactiveattrib Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* i965: Add an INTEL_DEBUG=spill option to test spillingJason Ekstrand2015-04-233-1/+3
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/debug: Use the ull specifier for DEBUG enum definesJason Ekstrand2015-04-231-31/+31
| | | | | | | The INTEL_DEBUG variable is a uint64_t and if we want a enum value higer than 32 bits, you need to use ull. We might as well use it for all of them. Reviewed-by: Matt Turner <[email protected]>
* i965: Disallow linear blits that are not cacheline aligned.Kenneth Graunke2015-04-231-8/+19
| | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. The main user, intel_emit_linear_blit, now handles this properly. But we might also have linear miptrees; just refuse to blit those. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.Kenneth Graunke2015-04-231-8/+14
| | | | | | | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. intel_emit_linear_blit needs to handle blits that are not cacheline aligned, as we use it for arbitrary glBufferSubData calls and subrange mappings. Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst pixel X offset field to represent the unaligned portion, and subtract that from the address so it's cacheline aligned. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* mapi: Adding missing string.h include.Pali Rohár2015-04-231-0/+2
| | | | | | | | File glapi_entrypoint.c calls memcpy() function, but does not include string.h header. So compilation can fail at error: implicit declaration of function 'memcpy'. Signed-off-by: Jose Fonseca <[email protected]>
* os/os_memory_aligned.h: Handle integer overflow.Jose Fonseca2015-04-231-1/+27
| | | | | | | | | | | This code is only used when our memory debugging wrappers are enabled, as we use the C runtime functions directly elsewhere. Tested llvmpipe on Windows w/ memory debugging enabled. VMware PR894263. Reviewed-by: Roland Scheidegger <[email protected]>
* draw: fix prim ids when there's no gsRoland Scheidegger2015-04-233-2/+15
| | | | | | | | | | | | | | | We were resetting the prim id count for each run of the prim assembler, hence this only worked when the draw calls were very small (the exact limit depending on the vertex size), since larger draw calls get split up. So, do the same as we do already if there's a gs, reset it to zero explicitly for every new instance (this possibly could use the same variable but that isn't doable without some heavy refactoring and I'm not sure it makes sense). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90130. Reviewed-by: Jose Fonseca <[email protected]> CC: <[email protected]>
* gallium/radeon: don't crash when getting out-of-bounds TEMP referencesMarek Olšák2015-04-231-0/+6
| | | | Reviewed-by: Tom Stellard <[email protected]>
* nir/lower_source_mods: Don't propagate register sourcesJason Ekstrand2015-04-221-0/+7
| | | | | | | | | The nir_lower_source_mods pass does a weak form of copy propagation to clean up all of the mov-with-negate's that get generated. However, we weren't properly checking that the sources were SSA and so we could end up moving a register read which is not, in general, valid. Reviewed-by: Connor Abbott <[email protected]>
* nir: Rewrite instr_rewrite_srcJason Ekstrand2015-04-221-24/+28
| | | | | | | The old code wasn't correctly handling the case where the new value of the source contains an indirect. Reviewed-by: Connor Abbott <[email protected]>
* nir/locals_to_regs: Hanadle indirect accesses of length-1 arraysJason Ekstrand2015-04-221-0/+8
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/locals_to_regs: Initialize registers with constant initializersJason Ekstrand2015-04-221-0/+103
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/locals_to_regs: Pass around the nir_shader rather than a void * mem_ctxJason Ekstrand2015-04-221-13/+13
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Add a simple growing array data structureJason Ekstrand2015-04-221-0/+96
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/types: Make glsl_get_length smarterJason Ekstrand2015-04-224-55/+8
| | | | | | | | | | | | | | | | | | Previously, this function returned the number of elements for structures and arrays and 0 for everything else. In NIR, this is almost never what you want because we also treat matricies as arrays so you have to special-case constantly. This commit glsl_get_length treat matrices as an array of columns by returning the number of columns instead of 0 This also fixes a bug in locals_to_regs caused by not checking for the matrix case in one place. v2: Only special-case for matrices and return a length of 0 for vectors as we did before. This was needed to not break the TGSI-based drivers and doesn't really affect NIR at the moment. Reviewed-by: Connor Abbott <[email protected]> Tested-by: Rob Clark <[email protected]>
* nir: Move get_const_initializer_load from vars_to_ssa to NIR coreJason Ekstrand2015-04-223-62/+65
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/lower_vars_to_ssa: Pass around the nir_shader instead of a void mem_ctxJason Ekstrand2015-04-221-14/+14
| | | | Reviewed-by: Connor Abbott <[email protected]>
* i965/nir: Use the correct offsets when handling register indirectsJason Ekstrand2015-04-221-27/+27
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/print: Print the closing paren on load_const instructionsJason Ekstrand2015-04-221-0/+2
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/tex: Use the correct return size for query_levels and lodJason Ekstrand2015-04-221-1/+4
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Refactor tex_instr_dest_size to use a switch statementJason Ekstrand2015-04-221-5/+8
| | | | Reviewed-by: Connor Abbott <[email protected]>
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