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* radv: Actually set the cmd_buffer usage_flags.Bas Nieuwenhuizen2017-09-041-0/+1
| | | | | | | | Otherwise, the simultaneous uage bit doesn't get set from the begin info, which we need for batchchaining. Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]>
* util: improve compiler guardEric Engestrom2017-09-033-6/+43
| | | | | | | | | | | | | | | Glibc 2.26 has dropped xlocale.h, but the functions needed (strtod_l() and strdof_l()) can be found in stdlib.h. Improve the detection method to allow newer builds to still make use of the locale-setting. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102454 Cc: Laurent Carlier <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Rob Herring <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Laurent Carlier <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* radeon/uvd: add Define Restart Interval to MJPEG bitstream reconstructionLeo Liu2017-09-021-0/+11
| | | | | | It adds the capacity to decode MJPEG stream with DRI marker Signed-off-by: Leo Liu <[email protected]>
* radeon/uvd: fix MJPEG quantization table indexLeo Liu2017-09-021-1/+1
| | | | | | Fixes: 130d1f456b8 ("radeon/uvd: reconstruct MJPEG bitstream") Signed-off-by: Leo Liu <[email protected]>
* st/mesa: fix view template initialization in try_pbo_readpixelsRoland Scheidegger2017-09-031-1/+1
| | | | | | | | | | | | I think this is what the code was meant to do, albeit as far as I can tell the redundant initialization some analyzers complain about should work as well just fine (only the first layer will be used, if the view contains one or more layers doesn't really matter). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102467 Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: [email protected]
* genxml: Make Border Color Pointer an address on Gen4-5, not an offset.Kenneth Graunke2017-09-024-9/+7
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Inline emit_reloc in __genx_combine_addressKenneth Graunke2017-09-021-12/+5
| | | | | | One less layer of baklava. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix crash in fallback GTT mapping.Kenneth Graunke2017-09-021-2/+4
| | | | | | | We can't perf_debug without a context. Cc: [email protected] Reviewed-by: Anuj Phogat <[email protected]>
* i965: Fix state flagging of Gen6 SOL programs.Kenneth Graunke2017-09-022-19/+6
| | | | | | | | | | | | | | | | | | | It doesn't seem like the old code could possibly work. 1. brw_gs_state_dirty made us bail unless one of these flags were set: _NEW_TEXTURE, BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_TRANSFORM_FEEDBACK 2. If there was no geometry program, we called brw_upload_ff_gs_prog()3 3. That checked brw_ff_gs_state_dirty and bailed unless these were set: _NEW_LIGHT, BRW_NEW_PRIMITIVE, BRW_NEW_TRANSFORM_FEEDBACK, BRW_NEW_VS_PROG_DATA. 4. brw_ff_gs_prog_key pv_first and attr fields were set based on data depending on _NEW_LIGHT and BRW_NEW_VS_PROG_DATA. This means that if we needed a FF GS program, and changed the VS outputs or provoking vertex mode, we'd fail to notice that we needed to emit a new program. Reviewed-by: Jordan Justen <[email protected]>
* i965: Drop useless gen6_brw_upload_ff_gs_prog() wrapper.Kenneth Graunke2017-09-023-7/+1
| | | | | | gen6...brw? Drop some baklava layers. Reviewed-by: Jordan Justen <[email protected]>
* freedreno: skip batch-cache for compute shadersRob Clark2017-09-021-7/+1
| | | | | | | | It is kind of pointless for compute, and avoids issues with apps kicking off more than 32 compute shaders at once. Signed-off-by: Rob Clark <[email protected]> Cc: "17.2" <[email protected]>
* m4: Use older autoconf 2.63 compatible ax_check_compile_flag.Vinson Lee2017-09-011-5/+5
| | | | | | | | CentOS 6 and RHEL 6 have autoconf 2.63. Fixes: e4b2b69e828c ("configure: Add and use AX_CHECK_COMPILE_FLAG") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Move BATCH_SZ define into intel_batchbuffer.c.Kenneth Graunke2017-09-012-1/+2
| | | | | | It's only used in one file. Reviewed-by: Chris Wilson <[email protected]>
* i965: Drop batch_size argument from brw_bufmgr_init().Kenneth Graunke2017-09-013-4/+3
| | | | | | This is dead code and hasn't been used in a long time. Reviewed-by: Chris Wilson <[email protected]>
* i965: Rename brw_bo::offset64 to gtt_offset.Chris Wilson2017-09-013-12/+35
| | | | | | | | | | | | | | | | | We can drop the meaningless "64" suffix - libdrm_intel originally had an "offset" field that was an "unsigned long" which was the wrong size, and we couldn't remove/alter that field without breaking ABI, so we had to add a uint64_t "offset64" field. "gtt_offset" is also more descriptive than "offset". (Patch originally written by Ken, but Chris suggested a better name and supplied the giant comment making up the bulk of the patch, so I changed the authorship to him.) Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965: Drop the BRW_BATCH_STRUCT macro.Kenneth Graunke2017-09-012-4/+1
| | | | | | | It's used in exactly one place these days, and not much simpler than just calling intel_batchbuffer_data directly. Reviewed-by: Chris Wilson <[email protected]>
* i965: Don't double count the batch in aperture_space.Kenneth Graunke2017-09-011-1/+1
| | | | | | | | | intel_batchbuffer_reset calls add_exec_bo on the batch right away, which adds in the batch BO size. Fixes: 29ba502a4e28 ("i965: Use I915_EXEC_BATCH_FIRST when available.") Reviewed-by: Chris Wilson <[email protected]>
* swr: Report format max_samples=1 to maintain support for "fake" msaa.Cherniak, Bruce2017-09-011-11/+11
| | | | | | | | | | | | | | | | | | | | Accompanying patch "st/mesa: only try to create 1x msaa surfaces for 'fake' msaa" requires driver to report max_samples=1 to enable "fake" msaa. Previously, 0 and 1 were treated equivalently in st_init_extensions() and either could enable "fake" msaa. This patch raises the swr default msaa_max_count from 0 to 1, so that swr_is_format_supported will report max_samples=1. Real msaa can still be enabled by exporting SWR_MSAA_MAX_COUNT with a pow2 value between 2 and 16. This patch is necessary to prevent an OpenSWR regression resulting from the st/mesa patch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102038 Acked-by: Brian Paul <[email protected]> Reviewed-By: George Kyriazis <[email protected]>
* aubinator: remove duplicate initialisationEric Engestrom2017-09-011-1/+0
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* radv: report VM faults if detectedSamuel Pitoiset2017-09-012-0/+16
| | | | | | | It's fairly simple for now, but this might be quite useful. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: move si_vm_fault_occured() to AMD common codeSamuel Pitoiset2017-09-013-102/+117
| | | | | | | | For radv, in order to report VM faults when detected. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_check_gpu_hangs() helper functionSamuel Pitoiset2017-09-013-12/+27
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: disassemble SPIR-V binaries with RADV_DEBUG=spirvSamuel Pitoiset2017-09-014-0/+39
| | | | | | | | | This introduces a new separate option because the output can be quite verbose. If spirv-dis is not found in the path, this debug option is useless. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: move RADV_TRACE_FILE functions to radv_debug.cSamuel Pitoiset2017-09-019-23/+80
| | | | | | | | | At the moment, debugging radv is not really easy because the driver doesn't report enough information when it hangs. This new file will be the main location for all debug tools. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: silent a compiler warning in radv_emit_framebuffer_state()Samuel Pitoiset2017-09-011-3/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: compute correct maximum wave count per SIMDSamuel Pitoiset2017-09-011-1/+12
| | | | | | | Ported from RadeonSI (original patch by Marek). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* st/mesa: only try to create 1x msaa surfaces for "fake" msaa driversBrian Paul2017-08-313-14/+24
| | | | | | | | | | | | | | | | | | | | For software drivers where we want "fake" msaa support for GL 3.x, we treat 1 sample as being msaa. For drivers with real msaa support, start format probing at 2x msaa. For drivers with fake msaa support, start format probing at 1x msaa. This also tweaks the MaxSamples code in st_init_extensions() so that we use MaxSamples=1 for fake msaa. This allows the format proble loops to run at least one iteration. This fixes a llvmpipe/VTK regression from commit 6839d3369905eb02151. And for drivers with fake msaa support, calls such as glTexImage2DMultisample(samples=1) will now succeed. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102038 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102125 Reviewed-by: Roland Scheidegger <[email protected]>
* nvc0/ir: propagate immediates to CALL input MOVsTobias Klausmann2017-08-311-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On using builtin functions we have to move the input to registers $0 and $1, if one of the input value is an immediate, we fail to propagate the immediate: ... mov u32 $r477 0x00000003 (0) ... mov u32 $r0 %r473 (0) mov u32 $r1 $r477 (0) call abs BUILTIN:0 (0) mov u32 %r495 $r1 (0) ... With this patch the immediate is propagated, potentially causing the first MOV to be superfluous, which we'd remove in that case: ... mov u32 $r0 %r473 (0) mov u32 $r1 0x00000003 (0) call abs BUILTIN:0 (0) mov u32 %r495 $r1 (0) ... Shaderdb stats: total instructions in shared programs : 4893460 -> 4893324 (-0.00%) total gprs used in shared programs : 582972 -> 582881 (-0.02%) total local used in shared programs : 17960 -> 17960 (0.00%) local gpr inst bytes helped 0 91 112 112 hurt 0 0 0 0 v2: implement some changes proposed by imirkin, the manual deletion of the dead mov is necessary after ea22ac23e0 ("nvc0/ir: unlink values pre- and post-call to division function") as the potentially dead mov is unlinked properly, causing later passes to not notice the mov op at all and thus not cleaning it up. That makes up a big chunk of the regression the above commit caused. Keep the deletion of the op where it is, deleting it later unnecessarily blows up size of the change. Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: write 0 to pipeline_statistics.cs_invocationsKarol Herbst2017-08-311-0/+1
| | | | | | | | | | | | | cs_invocations are currently unsupported, but leaving the field uninitialized is even worse. fixes on nvc0: * KHR-GL45.pipeline_statistics_query_tests_ARB.functional_default_qo_values * KHR-GL45.pipeline_statistics_query_tests_ARB.functional_non_rendering_commands_do_not_affect_queries Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 loadBen Crocker2017-09-011-2/+28
| | | | | | | | | | | | | | | | | | | | | | Fix loading of a 3x16 vector as a single 48-bit load on big-endian systems (PPC64, S390). Roland Scheidegger's commit e827d9175675aaa6cfc0b981e2a80685fb7b3a74 plus Ray Strode's patch reduce pre-Roland Piglit failures from ~4000 to ~2000. This patch fixes three of the four regressions observed by Ray: - draw-vertices - draw-vertices-half-float - draw-vertices-half-float_gles2 One regression remains: - draw-vertices-2101010 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100613 Cc: "17.2" "17.1" <[email protected]> Signed-off-by: Ben Crocker <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: correct channel shift logic on big endianRay Strode2017-09-011-1/+7
| | | | | | | | | | | | | | | | | | | lp_build_fetch_rgba_soa fetches a texel from a texture. Part of that process involves first gathering the element together from memory into a packed format, and then breaking out the individual color channels into separate, parallel arrays. The code fails to account for endianess when reading the packed values. This commit attempts to correct the problem by reversing the order the packed values are read on big endian systems. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100613 Cc: "17.2" "17.1" <[email protected]> Signed-off-by: Ray Strode <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* util: only use SCHED_IDLE in pthread_setschedparam() when it's definedRoland Scheidegger2017-09-011-1/+1
| | | | | | Fixes build error when it's not. Reviewed-by: Jose Fonseca <[email protected]>
* anv/formats: Nicely handle unknown VkFormat enumsJason Ekstrand2017-08-311-5/+14
| | | | | | | | | | | This fixes some crashes in the dEQP-VK.memory.requirements.core.* tests. I'm not sure whether or not passing out-of-bound formats into the query is supposed to be allowed but there's no harm in protecting ourselves from it. Reviewed-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/101956 Cc: [email protected]
* vbo: fix offset in minmax cache keyCharmaine Lee2017-08-301-3/+5
| | | | | | | | | | | | | Instead of saving primitive offset in the minmax cache key, save the actual buffer offset which is used in the cache lookup. Fixes rendering artifact seen with GoogleEarth when run with VMware driver. v2: Per Brian's comment, initialize offset to avoid compiler warning. Cc: [email protected] Reviewed-by: Brian Paul <[email protected]>
* anv: fix build errors on androidTapani Pälli2017-08-311-2/+3
| | | | | | | | | error: incompatible pointer to integer conversion initializing 'VkFence' (aka 'unsigned long long') with an expression of type 'void *' [-Werror,-Wint-conversion] Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* winsys/amdgpu: set AMDGPU_GEM_CREATE_VM_ALWAYS_VALID if possible v2Christian König2017-08-313-5/+27
| | | | | | | | | | | When the kernel supports it set the local flag and stop adding those BOs to the BO list. Can probably be optimized much more. v2: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: set a per-buffer flag that disables inter-process sharing (v4)Marek Olšák2017-08-314-28/+56
| | | | | | | | | | | For lower overhead in the CS ioctl. Winsys allocators are not used with interprocess-sharable resources. v2: It shouldn't crash anymore, but the kernel will reject the new flag. v3 (christian): Rename the flag, avoid sending those buffers in the BO list. v4 (christian): Remove setting the kernel flag for now Reviewed-by: Marek Olšák <[email protected]>
* i965: Use BLORP for buffer object stall avoidance blits instead of BLT.Kenneth Graunke2017-08-301-11/+11
| | | | | | | | Improves performance of GFXBench4 tests at 1024x768 on a Kabylake GT2: - Manhattan 3.1 by 1.32134% +/- 0.322734% (n=8). - Car Chase by 1.25607% +/- 0.291262% (n=5). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Always flush caches after blitting to a GL buffer object.Kenneth Graunke2017-08-301-1/+3
| | | | | | | | | | | | | | | | | When we blit data into a buffer object, we may need to invalidate any caches that might contain stale data, so the new data becomes visible. For example, if the buffer object is bound as a vertex buffer, we need to invalidate the vertex fetch cache. While this flushing was missing, it usually happened implicitly for non-obvious reasons: we're usually on the render ring, and calling intel_emit_linear_blit() would require switching to the BLT ring, causing an implicit flush. This likely provoked the kernel to do PIPE_CONTROLs on our behalf. Although, Gen4-5 wouldn't have this behavior. At any rate, we should do it ourselves. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().Kenneth Graunke2017-08-301-0/+1
| | | | | | | | | Although we're phasing out brw_emit_mi_flush(), we still use it in some places in order to "flush everything". In a number of those places, we write data to a buffer that we may then bind as an image surface, SSBO, or atomic buffer. Those usages require us to flush the data cache. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add a brw_blorp_copy_buffers() command.Kenneth Graunke2017-08-302-0/+29
| | | | | | | | This exposes the new blorp_copy_buffer() functionality to i965. It should be a drop-in replacement for intel_emit_linear_blit() (other than the arguments being backwards, for consistency with BLORP). Reviewed-by: Jason Ekstrand <[email protected]>
* blorp: Make blorp_buffer_copy work on Gen4-6.Kenneth Graunke2017-08-301-9/+10
| | | | | | Gen4-6 can only handle surfaces up to 8192. Only Gen7+ can do 16384. Reviewed-by: Jason Ekstrand <[email protected]>
* blorp: Turn anv_CmdCopyBuffer into a blorp_buffer_copy() helper.Kenneth Graunke2017-08-303-99/+143
| | | | | | | | | | | I want to be able to copy between buffer objects using BLORP in the i965 driver. Anvil already had code to do this, in a reasonably efficient manner - first using large bpp copies, then smaller bpp copies. This patch moves that logic into BLORP as blorp_buffer_copy(), so we can use it in both drivers. Reviewed-by: Jason Ekstrand <[email protected]>
* radv: don't assert on empty hash tableGrazvydas Ignotas2017-08-311-0/+3
| | | | | | | | | | | | | Currently if table_size is 0, it's falling through to: unreachable("hash table should never be full"); But table_size can be 0 when RADV_DEBUG=nocache is set, or when the table allocation fails (which is not considered an error). Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* svga: include sample count in surface_size() computationBrian Paul2017-08-301-1/+1
| | | | | | | Use MAX2() because sampleCount will be zero for non-MSAA surfaces. No Piglit regressions. Reviewed-by: Charmaine Lee <[email protected]>
* i965: drop unused brw->needs_unlit_centroid_workaroundLionel Landwerlin2017-08-302-11/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->has_surface_tile_offset in favor of devinfo'sLionel Landwerlin2017-08-305-8/+9
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->no_simd8Lionel Landwerlin2017-08-301-1/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->has_plnLionel Landwerlin2017-08-302-2/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->must_use_separate_stencil in favor of devinfo'sLionel Landwerlin2017-08-304-4/+5
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
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