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* anv: Drop some unneeded ANV_FROM_HANDLE for physical devicesJason Ekstrand2019-04-181-6/+0
* anv: Re-sort the GetPhysicalDeviceFeatures2 switch statementJason Ekstrand2019-04-181-17/+17
* radeonsi/gfx9: use the correct condition for the DPBB + QUANT_MODE workaroundMarek Olšák2019-04-181-4/+4
* nir/algebraic: Strength reduce some compares of x and -xIan Romanick2019-04-181-0/+3
* nir/algebraic: Fix some 1-bit Boolean weirdnessIan Romanick2019-04-181-0/+3
* nir/algebraic: Replace a pattern where iand with a Boolean is used as a bcselIan Romanick2019-04-181-0/+4
* nir/algebraic: Recognize open-coded copysign(1.0, a)Ian Romanick2019-04-181-0/+6
* intel/fs: Generate better code for fsign multiplied by a valueIan Romanick2019-04-181-0/+43
* intel/fs: Add a scale factor to emit_fsignIan Romanick2019-04-182-12/+77
* intel/fs: Refactor code generation for nir_op_fsign to its own functionIan Romanick2019-04-182-65/+65
* intel/fs: Eliminate dead code firstIan Romanick2019-04-181-0/+8
* freedreno: Fix format string warningKristian H. Kristensen2019-04-181-1/+1
* freedreno/a6xx: Add helper for incrementing regidKristian H. Kristensen2019-04-181-1/+10
* freedreno: Use enum values from matching enumKristian H. Kristensen2019-04-182-3/+3
* freedreno/a2xx: Fix redundant if statementKristian H. Kristensen2019-04-181-16/+14
* freedreno/ir3: Mark ir3_context_error() as NORETURNKristian H. Kristensen2019-04-182-3/+3
* nir: Add a nir_src_as_intrinsic() helperJason Ekstrand2019-04-185-51/+19
* nir: Rework nir_src_as_alu_instr to not take a pointerJason Ekstrand2019-04-184-26/+18
* nir: Drop "struct" from some nir_* declarationsJason Ekstrand2019-04-183-11/+11
* anv: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-181-0/+11
* i965: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-182-0/+6
* iris: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-182-0/+12
* anv/device: expose VK_KHR_shader_float16_int8 in gen8+Iago Toral Quiroga2019-04-182-0/+10
* anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+Iago Toral Quiroga2019-04-181-0/+2
* compiler/spirv: move the check for Int8 capabilityIago Toral Quiroga2019-04-181-4/+3
* intel/compiler: validate region restrictions for mixed float modeIago Toral Quiroga2019-04-182-0/+880
* intel/compiler: validate conversions between 64-bit and 8-bit typesIago Toral Quiroga2019-04-182-0/+105
* intel/compiler: validate region restrictions for half-float conversionsIago Toral Quiroga2019-04-182-1/+270
* intel/compiler: also set F execution type for mixed float mode in BDWIago Toral Quiroga2019-04-181-16/+20
* intel/compiler: implement SIMD16 restrictions for mixed-float instructionsIago Toral Quiroga2019-04-181-0/+72
* intel/compiler: skip MAD algebraic optimization for half-float or mixed modeIago Toral Quiroga2019-04-181-0/+4
* intel/compiler: remove inexact algebraic optimizations from the backendIago Toral Quiroga2019-04-181-38/+1
* intel/compiler: fix cmod propagation for non 32-bit typesIago Toral Quiroga2019-04-181-4/+9
* intel/compiler: add a brw_reg_type_is_integer helperIago Toral Quiroga2019-04-181-0/+18
* intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bitIago Toral Quiroga2019-04-181-0/+26
* intel/compiler: generalize the combine constants passIago Toral Quiroga2019-04-181-22/+212
* intel/eu: force stride of 2 on NULL register for Byte instructionsIago Toral Quiroga2019-04-181-0/+11
* intel/compiler: ask for an integer type if requesting an 8-bit typeIago Toral Quiroga2019-04-181-2/+3
* intel/compiler: rework conversion opcodesIago Toral Quiroga2019-04-181-19/+22
* intel/compiler: activate 16-bit bit-size lowerings also for 8-bitIago Toral Quiroga2019-04-181-1/+1
* intel/compiler: split is_partial_write() into two variantsIago Toral Quiroga2019-04-1811-30/+54
* intel/compiler: workaround for SIMD8 half-float MAD in gen8Iago Toral Quiroga2019-04-181-11/+28
* intel/compiler: fix ddy for half-float in BroadwellIago Toral Quiroga2019-04-181-2/+15
* intel/compiler: fix ddx and ddy for 16-bit floatIago Toral Quiroga2019-04-181-19/+18
* intel/compiler: set correct precision fields for 3-source float instructionsIago Toral Quiroga2019-04-181-0/+16
* intel/compiler: allow half-float on 3-source instructions since gen8Iago Toral Quiroga2019-04-181-1/+2
* intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bitsIago Toral Quiroga2019-04-181-1/+4
* intel/compiler: add new half-float register type for 3-src instructionsIago Toral Quiroga2019-04-181-0/+4
* intel/compiler: add instruction setters for Src1Type and Src2Type.Iago Toral Quiroga2019-04-181-0/+2
* intel/compiler: drop unnecessary temporary from 32-bit fsign implementationIago Toral Quiroga2019-04-181-3/+2
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