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* intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regsIago Toral Quiroga2018-12-202-2/+4
* st/mesa: remove sampler associated with buffer texture in pbo logicIlia Mirkin2018-12-201-5/+0
* gallivm: use llvm jit code for decoding s3tcRoland Scheidegger2018-12-207-383/+2239
* radv/query: Use 1-bit booleans in query shadersJason Ekstrand2018-12-191-21/+21
* radv/query: Add a nir_test_flag helperJason Ekstrand2018-12-191-15/+16
* freedreno/ir3: Handle GL_NONE in get_num_components_for_glformat()Eduardo Lima Mitev2018-12-191-3/+8
* docs: Add an encouraging note about providing reviews and acks.Eric Anholt2018-12-191-0/+8
* docs: Add a note that MRs should still include any r-b or a-b tags.Eric Anholt2018-12-191-0/+4
* v3d: Load and store aligned utiles all at once.Eric Anholt2018-12-191-8/+114
* v3d: Add a fallthrough path for utile load/store of 32 byte lines.Eric Anholt2018-12-191-12/+16
* vc4: Move the utile load/store functions to a header for reuse by v3d.Eric Anholt2018-12-194-202/+234
* v3d: Implement texture_subdata to reduce teximage upload copies.Eric Anholt2018-12-191-29/+85
* v3d: Remove dead prototypes for load/store utile functions.Eric Anholt2018-12-191-2/+0
* v3d: Don't try to create shadow tiled temporaries for 1D textures.Eric Anholt2018-12-191-1/+2
* v3d: Fix check for TFU job completion in the simulator.Eric Anholt2018-12-191-1/+1
* v3d: Put the dst bo first in the list of BOs for TFU calls.Eric Anholt2018-12-191-2/+2
* nir: properly find the entry to keep in copy_prop_varsCaio Marcelo de Oliveira Filho2018-12-191-3/+16
* winsys/amdgpu: Pull in LLVM CFLAGSMichel Dänzer2018-12-192-1/+2
* nir: properly clear the entry sources in copy_prop_varsCaio Marcelo de Oliveira Filho2018-12-191-0/+3
* docs: format code blocks a bit nicelyEric Engestrom2018-12-191-0/+3
* docs: add meson cross compilation instructionsEric Engestrom2018-12-191-0/+83
* virgl: move resource creation / import / destruction to common codeGurchetan Singh2018-12-194-114/+89
* virgl: move resource metadata into base resourceGurchetan Singh2018-12-194-91/+71
* virgl: modify how we handle GL_MAP_FLUSH_EXPLICIT_BITGurchetan Singh2018-12-194-69/+25
* virgl: make virgl_buffers use resource helpersGurchetan Singh2018-12-192-20/+11
* virgl: make transfer code with PIPE_BUFFER targetsGurchetan Singh2018-12-191-2/+4
* virgl: consolidate transfer codeGurchetan Singh2018-12-195-59/+73
* virgl: store layer_stride in metadataGurchetan Singh2018-12-192-6/+6
* virgl: move vrend_get_tex_image_offset to common codeGurchetan Singh2018-12-193-26/+28
* virgl: move virgl_resource_layout to common codeGurchetan Singh2018-12-193-42/+51
* virgl: move texture metadata to common codeGurchetan Singh2018-12-192-12/+18
* virgl: remove unnessecary codeGurchetan Singh2018-12-191-3/+0
* virgl: texture_transfer_pool --> transfer_poolGurchetan Singh2018-12-196-11/+11
* radeonsi: const-ify the si_query_opsNicolai Hähnle2018-12-193-5/+5
* radeonsi: split perfcounter queries from si_query_hwNicolai Hähnle2018-12-191-50/+93
* radeonsi: factor si_query_buffer logic out of si_query_hwNicolai Hähnle2018-12-194-110/+99
* radeonsi: move query suspend logic into the top-level si_query structNicolai Hähnle2018-12-193-44/+62
* radeonsi: move remaining perfcounter code into si_perfcounter.cNicolai Hähnle2018-12-197-766/+643
* radeonsi: track constant buffer bind history in si_pipe_set_constant_bufferNicolai Hähnle2018-12-191-2/+3
* radeonsi: use si_set_rw_shader_buffer for setting streamout buffersNicolai Hähnle2018-12-191-50/+11
* radeonsi: add an si_set_rw_shader_buffer convenience functionNicolai Hähnle2018-12-192-45/+64
* radeonsi: avoid using hard-coded SI_NUM_RW_BUFFERSNicolai Hähnle2018-12-191-1/+2
* radeonsi: show the fixed function TCS in debug dumpsNicolai Hähnle2018-12-191-2/+8
* radeonsi: const-ify si_set_tesseval_regsNicolai Hähnle2018-12-191-2/+2
* radeonsi: rename SI_RESOURCE_FLAG_FORCE_TILING to clarify its purposeNicolai Hähnle2018-12-193-4/+4
* radeonsi: don't set RAW_WAIT for CP DMA clearsNicolai Hähnle2018-12-191-1/+2
* radeonsi/gfx9: use SET_UCONFIG_REG_INDEX packets when availableNicolai Hähnle2018-12-194-5/+18
* radeonsi: add si_init_draw_functions and make some functions staticNicolai Hähnle2018-12-194-22/+22
* radeonsi: extract declare_vs_blit_inputsNicolai Hähnle2018-12-191-18/+25
* radeonsi: move SI_FORCE_FAMILY functionality to winsysNicolai Hähnle2018-12-192-34/+36
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