summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
* gk110/ir: emit load constant subopIlia Mirkin2014-07-241-0/+1
* mesa/st: add support for interpolate_at_* opsIlia Mirkin2014-07-241-3/+9
* nv50/ir: fix phi/union sources when their def has been mergedIlia Mirkin2014-07-241-0/+8
* nv50/ir: fix hard-coded TYPE_U32 sized registerIlia Mirkin2014-07-241-3/+4
* nvc0: mark shader header if fp64 is usedIlia Mirkin2014-07-241-0/+2
* nv50/ir: keep track of whether the program uses fp64Ilia Mirkin2014-07-242-2/+7
* nvc0: make sure that the local memory allocation is aligned to 0x10Ilia Mirkin2014-07-241-1/+1
* mesa: add ARB_clear_texture.xml to file list, remove duplicate declsIlia Mirkin2014-07-242-12/+1
* ilo: check the tilings of imported handlesChia-I Wu2014-07-241-30/+36
* ilo: clean up resource bo renamingChia-I Wu2014-07-244-51/+63
* ilo: share some code between {tex,buf}_create_boChia-I Wu2014-07-241-59/+55
* ilo: use native 3-component vertex formats on GEN7.5+Chia-I Wu2014-07-242-1/+6
* ilo: allow for device-dependent format translationChia-I Wu2014-07-245-32/+39
* i965: Accelerate uploads of RGBA and BGRA GL_UNSIGNED_INT_8_8_8_8_REV texturesJason Ekstrand2014-07-231-1/+5
* mesa: Fix the name in the error messageIan Romanick2014-07-231-1/+1
* glsl: Fix some bad indentationIan Romanick2014-07-231-3/+3
* i965/fs: Set LastRT on the final FB write on Broadwell.Kenneth Graunke2014-07-231-4/+2
* i965: Port INTEL_DEBUG=optimizer to the vec4 backend.Kenneth Graunke2014-07-231-6/+36
* i965: Save the gl_shader_stage enum in backend_visitor.Kenneth Graunke2014-07-232-1/+4
* i965: Don't print WE_normal in disassembly.Kenneth Graunke2014-07-231-1/+1
* freedreno/a3xx/compiler: fix p0 (kill, etc)Rob Clark2014-07-231-1/+2
* Revert "r600g/compute: Fix warnings"Tom Stellard2014-07-232-16/+12
* radeon/llvm: fix formattingGrigori Goronzy2014-07-231-10/+14
* radeon/llvm: enable unsafe math for graphics shadersGrigori Goronzy2014-07-231-0/+5
* r600g/compute: Fix warningsTom Stellard2014-07-232-12/+16
* r600g: Use hardware sqrt instructionGlenn Kennard2014-07-232-7/+4
* r600g/compute: Remove unneeded code from compute_memory_promote_itemBruno Jiménez2014-07-232-36/+12
* r600g/compute: Quick exit if there's nothing to add to the poolBruno Jiménez2014-07-231-0/+4
* r600g/compute: Defrag the pool if it's necesaryBruno Jiménez2014-07-232-17/+19
* r600g/compute: Add a function for defragmenting the poolBruno Jiménez2014-07-232-0/+28
* r600g/compute: Add a function for moving items in the poolBruno Jiménez2014-07-232-0/+93
* freedreno/a3xx: more vtx formatsRob Clark2014-07-231-0/+17
* freedreno/a3xx/compiler: const file relative addressingRob Clark2014-07-238-68/+203
* freedreno/a3xx/compiler: move functionRob Clark2014-07-231-35/+35
* freedreno/a3xx: add back a few stallsRob Clark2014-07-231-0/+8
* targets/dri: fix freedreno targetsRob Clark2014-07-232-3/+11
* freedreno: update generated headersRob Clark2014-07-234-14/+14
* docs: Update GL3.txt and relnotes for GL_ARB_clear_textureNeil Roberts2014-07-232-1/+2
* meta: Add a meta implementation of GL_ARB_clear_textureNeil Roberts2014-07-234-0/+198
* meta: Add a state flag for the GL_DITHERNeil Roberts2014-07-232-0/+12
* texstore: Add a generic implementation of GL_ARB_clear_textureNeil Roberts2014-07-232-0/+79
* mesa/main: Add generic bits of ARB_clear_texture implementationNeil Roberts2014-07-233-1/+271
* teximage: Add utility func for format/internalFormat compatibility checkNeil Roberts2014-07-231-21/+38
* mesa/main: add ARB_clear_texture entrypointsIlia Mirkin2014-07-237-1/+69
* r600g/radeonsi: Use write-combined CPU mappings of some BOs in GTTMichel Dänzer2014-07-2317-26/+77
* winsys/radeon: Use separate caching buffer managers for VRAM and GTTMichel Dänzer2014-07-233-9/+20
* docs/GL3.txt: update status for ARB_compute_shaderDave Airlie2014-07-231-1/+1
* mesa: Don't use memcpy() in _mesa_texstore() for float depth texture dataAnuj Phogat2014-07-211-0/+15
* i965/fs: Fix gl_SampleMask handling for SIMD16 on Gen8+.Kenneth Graunke2014-07-211-5/+0
* i965/fs: Fix gl_SampleID for 2x MSAA and SIMD16 mode.Kenneth Graunke2014-07-213-1/+11
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 14:22:54 +0000