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* softpipe: remove unused softpipe_context::line_stipple_counterBrian Paul2017-06-201-2/+0
| | | | Trivial.
* radeonsi: set correct usage flag according to image access typeSamuel Pitoiset2017-06-201-1/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: fix a deadlock when waiting for submission_in_progressMarek Olšák2017-06-202-16/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First this happens: 1) amdgpu_cs_flush (lock bo_fence_lock) -> amdgpu_add_fence_dependency -> os_wait_until_zero (wait for submission_in_progress) - WAITING 2) amdgpu_bo_create -> pb_cache_reclaim_buffer (lock pb_cache::mutex) -> pb_cache_is_buffer_compat -> amdgpu_bo_wait (lock bo_fence_lock) - WAITING So both bo_fence_lock and pb_cache::mutex are held. amdgpu_bo_create can't continue. amdgpu_cs_flush is waiting for the CS ioctl to finish the job, but the CS ioctl is trying to release a buffer: 3) amdgpu_cs_submit_ib (CS thread - job entrypoint) -> amdgpu_cs_context_cleanup -> pb_reference -> pb_destroy -> amdgpu_bo_destroy_or_cache -> pb_cache_add_buffer (lock pb_cache::mutex) - DEADLOCK The simple solution is not to wait for submission_in_progress, which we need in order to create the list of dependencies for the CS ioctl. Instead of building the list of dependencies as a direct input to the CS ioctl, build the list of dependencies as a list of fences, and make the final list of dependencies in the CS thread itself. Therefore, amdgpu_cs_flush doesn't have to wait and can continue. Then, amdgpu_bo_create can continue and return. And then amdgpu_cs_submit_ib can continue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101294 Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: update all resident texture descriptors when neededSamuel Pitoiset2017-06-201-57/+104
| | | | | | | | | | | | | | | To avoid useless DCC fetches when DCC is disabled, descriptors have to be updated in order to reflect this change. This is quite similar to how we update descriptors of bound textures. As a side effect, this should also prevent VM faults when bindless textures are invalidated, because the VA in the descriptor has to be updated accordingly as well. I don't see any performance improvements with DOW3. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: keep track of the sampler state for texture handlesSamuel Pitoiset2017-06-202-0/+2
| | | | | | | | Needed for updating all resident texture descriptors when dirty_tex_counter changes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: perf: use gen_device_info rather then brw_contextLionel Landwerlin2017-06-191-3/+4
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: common: add number of thread per euLionel Landwerlin2017-06-192-2/+28
| | | | | | | This will be used by to normalize OA counters. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: common: express timestamps units in frequencyLionel Landwerlin2017-06-194-13/+15
| | | | | | | | | | | | | | Rather than storing the period as a double that looses some precision. Also fixes the Gen9LP timestamp frequency which is no 19200123 but 19200000 as pointed by Ville : https://lists.freedesktop.org/archives/intel-gfx/2017-April/125126.html Finally add the Cannonlake timestamp frequency. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: convert MI_REPORT_PERF_COUNT to genxmlLionel Landwerlin2017-06-193-28/+34
| | | | | | | Also make it available from gen7 only to gen7+. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: fix codegen with single operand equationLionel Landwerlin2017-06-191-1/+3
| | | | | | | | We did support single value operand equations, but not single variable operand ones. In particular we were failing on "$Sampler0Bottleneck". Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: common: add flag to identify platforms by nameLionel Landwerlin2017-06-192-6/+24
| | | | | | | | The perf infrastructure needs to identify specific platforms, not just generations. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/wm: Use stored hiz surface instead of creating copyTopi Pohjolainen2017-06-193-86/+2
| | | | | | | Now the last user of intel_miptree_get_aux_isl_surf() is gone. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use hiz surface instead of creating copyTopi Pohjolainen2017-06-191-14/+10
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree/gen7+: Use isl for hiz layoutsTopi Pohjolainen2017-06-197-245/+33
| | | | | | | v2: Use better assert by checking isl_surf_get_hiz_surf() Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Drop BO_ALLOC_FOR_RENDER in intel_miptree_alloc_mcs()Topi Pohjolainen2017-06-191-1/+6
| | | | | | | because buffers get unconditionally initialised by cpu writing. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use isl for mcs layoutsTopi Pohjolainen2017-06-193-88/+21
| | | | | | | | | | | and pass the ccs isl surface to blorp instead of creating a copy. v2 (Jason): Explain ccs change and use better assert checking isl_surf_get_mcs_surf() Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Refactor aux surface allocationTopi Pohjolainen2017-06-191-18/+36
| | | | | | | | | v2 (Jason): Drop unused argument in intel_alloc_aux_buffer() and move assignment of "buf->surf" in intel_alloc_aux_buffer() into this patch. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Use isl for hizTopi Pohjolainen2017-06-194-40/+27
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Refactor isl aux usage resolverTopi Pohjolainen2017-06-194-22/+41
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Use isl for stencil surfacesTopi Pohjolainen2017-06-192-19/+19
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Prepare range getter for isl basedTopi Pohjolainen2017-06-191-1/+8
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Prepare stencil mapping for isl basedTopi Pohjolainen2017-06-191-4/+28
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Prepare for isl based miptreesTopi Pohjolainen2017-06-191-2/+7
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Add isl based miptree creatorTopi Pohjolainen2017-06-191-0/+72
| | | | | | | | v2: Use new brw_bo_alloc_tiled() interface Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Add option to resolve offsets using isl_surfTopi Pohjolainen2017-06-191-0/+19
| | | | | | | | v2 (Nanley): Add comment telling why "level -= mt->first_level" Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Prepare slice copy for isl based miptreesTopi Pohjolainen2017-06-191-6/+22
| | | | | | | | | v2 (Jason): Fix a helper variable only used for assert - open code instead. Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/tex: Prepare image update for isl based miptreesTopi Pohjolainen2017-06-191-3/+16
| | | | | | Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Prepare framebuffer validator for isl based miptreesTopi Pohjolainen2017-06-191-3/+30
| | | | | | Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Prepare slice validator for isl based miptreesTopi Pohjolainen2017-06-192-11/+23
| | | | | | | | | v2 (Nanley): Minify depth in case of 3D surface. Also moved to .c file to get minify() without additional header inclusions Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Prepare image validation for isl based miptreesTopi Pohjolainen2017-06-191-0/+15
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Prepare up/downsampling for isl based miptreesTopi Pohjolainen2017-06-191-8/+38
| | | | | Reviewed-by: Nanley Chery <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Add isl surfaceTopi Pohjolainen2017-06-191-0/+2
| | | | | Reviewed-by: Nanley Chery <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Add helper for converting isl tiling to bufmgr tilingTopi Pohjolainen2017-06-191-0/+13
| | | | | Reviewed-by: Nanley Chery <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Refactor mapping table allocTopi Pohjolainen2017-06-191-2/+28
| | | | | | | v2 (Nanley): Use minify() instead of direct shift Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Declare minify(depth, level) layers for 3D stencilTopi Pohjolainen2017-06-191-1/+3
| | | | | | | | | Keeps following patch refactoring the table allocation non-functional. Suggested-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen4: Add support for single layer in alignment workaroundTopi Pohjolainen2017-06-197-11/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On gen < 6 one doesn't have level or layer specifiers available for render and depth targets. In order to support rendering to specific level/layer, driver needs to manually offset the surface to the desired slice. There are, however, alignment restrictions to respect as well and in come cases the only option is to use temporary single slice surface which driver copies after rendering to the full miptree. Current alignment workaround introduces new texture images which are added to the parent texture object. Texture validation later on copies the additional levels back to the surface that contains the full mipmap. This only works for non-arrayed surfaces and driver currently creates new arrayed images in vain - individual layers within the newly created are still unaligned the same as before. This patch drops this mechanism and instead attaches single temporary slice into the render buffer. This gets immediately copied back to the mipmapped and/or arrayed surface just after the render is done. Sitting on top of earlier series cleaning up the depth buffer state, this patch additionally fixes the following piglit tests: arb_framebuffer_object.fbo-generatemipmap-cubemap.g965m64 arb_texture_cube_map.copyteximage cube.g965m64 arb_texture_cube_map.copyteximage cube.ilkm64 arb_pixel_buffer_object.texsubimage array pbo.g965m64 ext_framebuffer_object.fbo-cubemap.g965m64 ext_texture_array.copyteximage 1d_array.g45m64 ext_texture_array.copyteximage 1d_array.g965m64 ext_texture_array.copyteximage 1d_array.ilkm64 ext_texture_array.copyteximage 2d_array.g45m64 ext_texture_array.copyteximage 2d_array.g965m64 ext_texture_array.copyteximage 2d_array.ilkm64 ext_texture_array.fbo-array.g965m64 ext_texture_array.fbo-generatemipmap-array.g965m64 ext_texture_array.gen-mipmap.g965m64 Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Separate src and dst slice specifiers in slice copyTopi Pohjolainen2017-06-191-25/+35
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Clarify face/level/layer in slice copyTopi Pohjolainen2017-06-191-19/+20
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* anv: Fix L3 cache programming on Bay TrailJonas Kulla2017-06-191-1/+1
| | | | | | | | | | | Valid values for URBAllocation start at 32, so substract that before programming the register. This was missed when porting from the GL driver. Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: fix dumping shader descriptors into ddebug logsMarek Olšák2017-06-191-35/+41
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a workaround for inexact SNORM8 blitting againMarek Olšák2017-06-191-0/+37
| | | | | | | | GFX9 is affected. We only have tests for GL_x_SNORM where x is R8, RG8, RGB8, and RGBA8. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix TC-compatible stencil compressionMarek Olšák2017-06-192-2/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix TXF_LZ with 1D texturesMarek Olšák2017-06-191-1/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: disable sparse buffersMarek Olšák2017-06-191-0/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/sid.h: don't use parentheses in PKT3_RELEASE_MEM definitionMarek Olšák2017-06-191-1/+1
| | | | | | | The parses skips the line if it contains parentheses. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: parse EVENT_WRITE_EOP, RELEASE_MEM, WAIT_REG_MEM, NOWHEREMarek Olšák2017-06-192-0/+47
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: simplify returning GL_VENDORMarek Olšák2017-06-192-5/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: remove the "Gallium 0.4 on" prefix from GL_RENDERERMarek Olšák2017-06-192-8/+1
| | | | | | | | | | | | | If you want to keep it for your driver, please raise your hand. The prefix will probably have to be added into the driver instead of here. I cringe when I look at my long renderer string: Gallium 0.4 on AMD Radeon R9 Fury Series (DRM 3.17.0 / 4.11.0-staging-01277-gab25a9e, LLVM 5.0.0) I'm sincerely sorry for all apps that detect Mesa by expecting "Gallium" in the string. Reviewed-by: Eric Anholt <[email protected]>
* st/mesa: don't update MSAA states for GL_FRAMEBUFFER_SRGBMarek Olšák2017-06-191-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Ignore anisotropic filtering in nearest mode.Kenneth Graunke2017-06-191-2/+4
| | | | | | | | | | | | | | | This fixes both Europa Universalis IV and Stellaris rendering on i965. This was tested on SKL. This fix was discovered by Jakub Szuppe at Stream HPC (https://streamhpc.com/). bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96958 bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95530 Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Dylan Baker <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: 17.1 <[email protected]>
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