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* automake: remove empty GALLIUM_PIPE_LOADER_LIBSEmil Velikov2015-07-1311-21/+7
| | | | | | Cc: Rob Clark <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* automake: pipe-loader: remove the 'client' pipe-loaderEmil Velikov2015-07-134-39/+22
| | | | | | | | | | Was only around as opencl's pipe-loader wanted to link against xcb in some cases. Cc: Rob Clark <[email protected]> Cc: Tom Stellard <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* pipe-loader: remove pipe_loader_drm_probe_fd() x_auth argumentEmil Velikov2015-07-136-90/+7
| | | | | | | | No longer used by anyone, as of last commit. Cc: Tom Stellard <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* pipe-loader: simplify pipe_loader_drm_probeEmil Velikov2015-07-131-9/+4
| | | | | | | | Do not iterate and (attempt to) open the render device, if we're over the requested number of devices. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* pipe-loader: drop support for non-render node devicesEmil Velikov2015-07-131-59/+1
| | | | | | | | | | | | | | | | | Render nodes have been around for quite some time. Removing support via the master/primary node allows us to clean up the conditional compilation and simplify the build greatly. For example currently we the pipe-loader, which explicitly links against xcb and friends (for X auth) if found at compile-time. That would cause problems as one will be forced to use X/xcb, even if it's a headless system that is used for opencl. v2: Clarify the linking topic in the commit message. Cc: Tom Stellard <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* radeonsi: direct emit intrinsic for DFRAC.Dave Airlie2015-07-131-0/+1
| | | | | | Michel reported this still failed, and this fixed it Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: ARB_gpu_shader_fp64 + ARB_vertex_attrib_64bit support.Dave Airlie2015-07-126-15/+175
| | | | | | | | | | | | This adds the translation from TGSI to AMDGPU llvm backend, for the 64-bit opcodes. The backend pretty much handles everything for us fine. There is one patch required for SI DFRAC support, that I know off. [airlied: fixed missing comma, updated relnotes] Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* loader: don't leak udev_enumerateGuillaume Desmottes2015-07-111-0/+4
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90073 Signed-off-by: Guillaume Desmottes <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* dri3_open: don't leak the replyGuillaume Desmottes2015-07-111-0/+2
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90073 Signed-off-by: Guillaume Desmottes <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* doxygen: Remove doxygen_sqlite3.db with 'make clean'Rhys Kidd2015-07-111-0/+1
| | | | | Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* doxygen: Add doxygen_sqlite3.db to .gitignoreRhys Kidd2015-07-111-0/+1
| | | | | Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* docs: add news item and link release notes for mesa 10.6.2Emil Velikov2015-07-112-0/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: Add sha256 checksums for the 10.6.2 releaseEmil Velikov2015-07-111-1/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 89cbd91b17989ec7eb1cb93ac427a84dca56cd79)
* Add release notes for the 10.6.2 releaseEmil Velikov2015-07-111-0/+164
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 9643cce94c8a1938e3342fb83d025a1e5c2aa79b)
* tgsi: add DFMA to the opcode infer functions.Dave Airlie2015-07-111-0/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g: move sampler/ubo index registers before temp regDave Airlie2015-07-111-7/+6
| | | | | | | | | | | temp_reg needs to be last, as we increment things away from it, otherwise on cayman some tests were overwriting the index regs. Fixes 2 piglit with ARB_gpu_shader5 forced on cayman. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix sampler/ubo indexing on caymanDave Airlie2015-07-112-6/+18
| | | | | | | | | | Cayman needs a different method to upload the CF IDX0/1 This fixes 31 piglits when ARB_gpu_shader5 is forced on with cayman. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50, nvc0: enable at least one color RT if alphatest is enabledIlia Mirkin2015-07-102-0/+36
| | | | | | | | | Fixes the following piglits: fbo-alphatest-nocolor fbo-alphatest-nocolor-ff Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* i965: Remove special case for layered drawbuffer attachments.Kenneth Graunke2015-07-101-1/+2
| | | | | | | | When binding a layered texture, the layer is already 0. There's no need to special case this. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/gen6: Set up layer constraints properly for depth buffers.Kenneth Graunke2015-07-101-1/+5
| | | | | | | | | | This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c from commit 77d55ef4819436ebbf9786a1e720ec00707bbb19. No Piglit changes on Sandybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Label the repclear shader "meta repclear" rather than "meta clear".Kenneth Graunke2015-07-101-1/+1
| | | | | | | | | | | | | | Color clears can be performed via two separate shaders - one is the generic "meta clear" shader (in meta.c); the other is the i965 specific "repclear" shader (in brw_meta_fast_clear.c). Giving them separate names makes them distinguishable when reading INTEL_DEBUG=shader_time output. v2: Call it "meta repclear", as suggested by Jason. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix indentation in emit_control_data_bits().Kenneth Graunke2015-07-101-72/+70
| | | | | | | The last patch left the code indented too far. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/gs: Move vertex_count != 0 check up a level; skip one caller.Kenneth Graunke2015-07-101-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Paul's original code had emit_control_data_bits() skip the URB write if vertex_count was 0. This meant wrapping every control data write in a conditional write. We accumulate control data bits in a single UD (32-bit) register. For simple shaders that don't emit many vertices, the control data header will be <= 32-bits long, so we only need to write it once at the end of the shader. For shaders with larger headers, we write out batches of control data bits at EmitVertex(), when (vertex_count * bits_per_vertex) % 32 == 0. On the first EmitVertex() call, the above expression will evaluate to true simply because vertex_count == 0. But we want to avoid emitting the control data bits, because we haven't accumulated 32-bits worth yet. In other words, the vertex_count != 0 check is really only necessary in the EmitVertex() batching case, not the end-of-thread case. This saves a CMP/IF/ENDIF in every shader that uses EndPrimitive() or multiple streams. The only downside is that a shader which emits no vertices at all will execute an additional URB write---but such shaders are pointless and not worth optimizing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: use set rather than old hash table for ir_validateTimothy Arceri2015-07-111-12/+12
| | | | | | | | | | When the new hash table implementation was added to Mesa it claimed to be much faster, see commits 35fd61bd99c1 and 72e55bb6888ff. The set implementation follows the same implementation strategy so this should be faster and there was no need to store a data field. Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Fix generation of git_sha1.h.tmp for gitlinksChad Versace2015-07-101-1/+4
| | | | | | | | | | | | | Don't assume that $(top_srcdir)/.git is a directory. It may be a gitlink file [1] if $(top_srcdir) is a submodule checkout or a linked worktree [2]. [1] A "gitlink" is a text file that specifies the real location of the gitdir. [2] Linked worktrees are a new feature in Git 2.5. Cc: "10.6, 10.5" <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* freedreno/a4xx: occlusion query supportRob Clark2015-07-101-1/+85
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-07-1011-57/+116
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: fixup new instr's blockRob Clark2015-07-101-0/+4
| | | | | | | | | | | | If we split addr/pred, the original instruction could have originated from a different block. If we don't fixup the block ptr we hit asserts later (in debug builds). NOTE: perhaps we don't want to try to preserve addr/pred reg's across block boundaries.. this at least needs some thought in case addr/pred writes end up inside a conditional block.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/ra: fix failed assert for a0/p0Rob Clark2015-07-101-0/+5
| | | | | | | | The address and predicate register are special, they don't get assigned in RA. So do a better job of ignoring them rather than hitting later asserts. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: shader-db tracesRob Clark2015-07-107-8/+67
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix crash in fd_invalidate_resource()Rob Clark2015-07-101-2/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* vc4: unref old fenceRob Clark2015-07-101-0/+2
| | | | | | | | | Some, but not all, state trackers will explicitly unref (and set to NULL) the previous *fence before calling pipe->flush(). So driver should use fence_ref() which will unref the old fence if not NULL. Signed-off-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]>
* ilo: unref old fenceRob Clark2015-07-101-0/+2
| | | | | | | | | Some, but not all, state trackers will explicitly unref (and set to NULL) the previous *fence before calling pipe->flush(). So driver should use fence_ref() which will unref the old fence if not NULL. Signed-off-by: Rob Clark <[email protected]> Acked-by: Chia-I Wu <[email protected]>
* freedreno: unref old fenceRob Clark2015-07-101-1/+3
| | | | | | | | Some, but not all, state trackers will explicitly unref (and set to NULL) the previous *fence before calling pipe->flush(). So driver should use fence_ref() which will unref the old fence if not NULL. Signed-off-by: Rob Clark <[email protected]>
* gallium: clarify reference counting for fenceRob Clark2015-07-101-1/+7
| | | | | | | | | Nowhere was it spelled out that the state tracker may expect the pipe driver to unref the old fence. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* xa: don't leak fencesRob Clark2015-07-103-3/+7
| | | | | | | | | | | | XA was never unref'ing last_fence in the various call paths to pipe->flush(). Add this to xa_context_flush() and update the other open-coded calls to pipe->flush() to use xa_context_flush() instead. This fixes a memory leak reported with xf86-video-freedreno. Reported-by: Nicolas Dechesne <[email protected]> Cc: "10.5 10.6" <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* i965/vs: Get rid of brw_vs_compile completely.Kenneth Graunke2015-07-093-40/+31
| | | | | | | | | After tearing it out another level or two, and just passing the key and vp directly, we can finally remove this struct. It also eliminates a pointless memcpy() of the key. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vs: Remove 'c'/vs_compile from vec4_vs_visitor.Kenneth Graunke2015-07-094-15/+15
| | | | | | | | | At this point, the brw_vs_compile structure only contains the key and gl_vertex_program pointer. We may as well pass and store them directly; it's simpler and more convenient (key-> instead of vs_compile->key...). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Move c->last_scratch into vec4_visitor.Kenneth Graunke2015-07-098-22/+15
| | | | | | | | | | | | Nothing outside of vec4_visitor uses it, so we may as well keep it internal. Commit db9c915abcc5ad78d2d11d0e732f04cc94631350 for the vec4 backend. (The empty class will be going away soon.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Move total_scratch calculation into the visitor.Kenneth Graunke2015-07-093-10/+7
| | | | | | | | This is more consistent with how we do it in the FS backend, and reduces a tiny bit of duplication. It'll also allow for a bit more tidying. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Move perf_debug about register spilling into the visitor.Kenneth Graunke2015-07-093-11/+13
| | | | | | | | | | | | This patch makes us only issue the performance warning about register spilling if we actually spilled registers. We also use scratch space for indirect addressing and the like. This is basically commit c51163b0cf7aff0375b1a5ea4cb3da9d9e164044 for the vec4 backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Plumb log_data through so the backend_shader field gets set.Kenneth Graunke2015-07-098-8/+18
| | | | | | | | | | Jason plumbed this through a while back in the FS backend, but apparently we were just passing NULL in the vec4 backend. This patch passes brw in as intended. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Switch on shader stage in nir_setup_outputs().Kenneth Graunke2015-07-091-26/+33
| | | | | | | | | Adding new shader stages to a switch statement is less confusing than an if-else-if ladder where all but the first case are fragment shader specific (but don't claim to be). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* tgsi: whitespace fixes in tgsi_parse.cBrian Paul2015-07-091-13/+13
| | | | Trivial.
* gallium: fix comment typo in p_shader_tokens.hBrian Paul2015-07-091-1/+1
|
* gallium/docs: s/treaded/treated/ typo in tgsi.rstBrian Paul2015-07-091-1/+1
| | | | Trivial.
* util: Don't link to SHA1 library if shader-cache is disabled.Matt Turner2015-07-091-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Set brw->batch.emit only #ifdef DEBUG.Matt Turner2015-07-092-1/+3
| | | | | | | | | | | | | | | It's only used inside #ifdef DEBUG. Cuts ~1.7k of .text, and more importantly prevents a larger code size regression in the next commit when the .used field is replaced and calculated on demand. text data bss dec hex filename 4945468 195152 26192 5166812 4ed6dc i965_dri.so before 4943740 195152 26192 5165084 4ed01c i965_dri.so after And surround the emit and total fields with #ifdef DEBUG to prevent such mistakes from happening again. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/hsw: Implement end of batch workaroundBen Widawsky2015-07-092-2/+29
| | | | | | | | | | | | | | | | | | | | This patch can cause an infinite recursion if the previous patch titled, "i965: Track finished batch state" isn't present (backporters take notice). v2: Sent out the wrong patch originally. This patches switches the order of flushes, doing the generic flush before the CC_STATE, and the required workaround flush afterwards v3: Only perform workaround for render ring Add text to the BATCH_RESERVE comments v4 (By Ken): Rebase; update citation to mention PRM and Wa name; combine two blocks. http://otc-mesa-ci.jf.intel.com/job/bwidawsk/171/ Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/vdpau: fix mixer size checksChristian König2015-07-091-11/+11
| | | | | | | | We need to check what the 3D pipe is able to handle for the mixer, not what the decoder is able to decode. This fixes output of resolutions like 720x1280. Signed-off-by: Christian König <[email protected]> CC: [email protected]
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