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* vc4: Allow RCL blits to the edge of the surface.Eric Anholt2015-12-081-2/+8
* vc4: Add disabled debug printf for describing blits.Eric Anholt2015-12-081-0/+10
* vc4: Fix check for tile RCL blits with mismatched y.Eric Anholt2015-12-081-1/+1
* vc4: Fix compiler warning from size_t change.Eric Anholt2015-12-081-1/+1
* scons: support for LLVM 3.7.Olivier Pena2015-12-081-1/+13
* docs/GL3.txt: consolidate r600 GL4.1.Dave Airlie2015-12-081-4/+4
* i965: Make uniform offsets be in terms of bytesJason Ekstrand2015-12-076-22/+49
* i965/nir_uniforms: Replace comps_per_unit with an is_scalar booleanJason Ekstrand2015-12-071-13/+15
* i965/nir: Remove unused indirect handlingJason Ekstrand2015-12-071-33/+11
* i965/state: Get rid of dword_pitch arguments to buffer functionsJason Ekstrand2015-12-076-38/+19
* i965/vec4: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-073-27/+7
* i965/fs: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-073-16/+13
* i965/vec4: Use byte offsets for UBO pulls on Sandy BridgeJason Ekstrand2015-12-073-10/+31
* i965: Fix texture views of 2d array surfacesBen Widawsky2015-12-071-2/+2
* radeonsi: last_gfx_fence is a winsys fenceNicolai Hähnle2015-12-071-1/+1
* nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integersIlia Mirkin2015-12-073-12/+11
* gk110/ir: fix imad sat/hi flag emission for immediate argsIlia Mirkin2015-12-071-8/+3
* i965: Add brw_device_info::min_ds_entries field.Kenneth Graunke2015-12-072-0/+12
* i965: Add state bits for tess stagesChris Forbes2015-12-074-2/+28
* i965: Add backend structures for tess stagesChris Forbes2015-12-076-0/+98
* i965: Set core tessellation-related limitsChris Forbes2015-12-071-2/+6
* i965: Request lowering of gl_TessLevel* from float[] to vec4s.Kenneth Graunke2015-12-071-0/+2
* i965: Create new files for HS/DS/TE state upload code.Kenneth Graunke2015-12-0710-110/+271
* gk104/ir: sampler doesn't matter for txfIlia Mirkin2015-12-071-1/+1
* radeonsi: disable DCC on StoneyMarek Olšák2015-12-071-0/+4
* winsys/amdgpu: addrlib - port a Fiji bug fixSonny Jiang2015-12-072-1/+46
* winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatibleSonny Jiang2015-12-072-2/+5
* winsys/amdgpu: addrlib - port fix error for workaround for 1D tilingSonny Jiang2015-12-071-1/+1
* st/va: disable MPEG4 by default v2Christian König2015-12-072-1/+15
* st/va: move HEVC functions into separate file v2Christian König2015-12-074-168/+215
* mesa: remove _mesa_tex_target_is_arrayAlejandro Piñeiro2015-12-072-17/+0
* i965: use _mesa_is_array_texture instead of _mesa_tex_target_is_arrayAlejandro Piñeiro2015-12-072-2/+2
* gk110/ir: fix imul hi emission with limm argIlia Mirkin2015-12-071-2/+2
* svga: use the debug callback to report issues to the state trackerBrian Paul2015-12-076-0/+62
* gallium/util: check callback pointers for non-null in pipe_debug_message()Brian Paul2015-12-071-3/+5
* i965: Add defines for gather push constantsAbdiel Janulgue2015-12-071-0/+19
* mesa: move GLES checks for SSO input/output validationTimothy Arceri2015-12-071-22/+23
* mesa: move GL_INVALID_OPERATION error to rendering callTimothy Arceri2015-12-073-25/+15
* mesa: move pipeline input/output validation inside _mesa_validate_program_pip...Timothy Arceri2015-12-071-15/+15
* glsl: re-validate program pipeline after sampler changeTimothy Arceri2015-12-071-0/+4
* r600: apply SIMD workaround to cayman also.Dave Airlie2015-12-071-1/+8
* r600: fix regression introduced with ring emit changes.Dave Airlie2015-12-071-1/+2
* r600: remove stale tessellation commentDave Airlie2015-12-071-1/+0
* docs: consolidate r600 entry in GL3.txtDave Airlie2015-12-071-14/+14
* docs: update with r600 tessellation status.Dave Airlie2015-12-072-1/+2
* r600: enable tessellation for evergreen/cayman (v2)Dave Airlie2015-12-071-1/+9
* r600g: reduce number of ps thread on caicosDave Airlie2015-12-071-1/+1
* r600g: adjust ls/hs thread counts for sumoDave Airlie2015-12-071-4/+4
* r600/asm: enable nstack check for tess ctrl/eval shaders.Dave Airlie2015-12-071-1/+1
* r600/asm: handle lds read operations.Dave Airlie2015-12-071-1/+21
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