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* glsl: add version checks to conditionals for builtin variable enablementIlia Mirkin2015-06-181-5/+5
| | | | | | | | | A number of builtin variables have checks based on the extension being enabled, but were missing enablement via a higher GLSL version. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Cc: "10.5 10.6" <[email protected]>
* glsl: handle conversions to double when comparing param matchesIlia Mirkin2015-06-181-3/+5
| | | | | | | | | This allows mod(int, int) to become selected as float mod when doubles are supported. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: "10.6" <[email protected]>
* ilo: remove missing ilo_fence.h from the sources listEmil Velikov2015-06-181-1/+0
| | | | Signed-off-by: Emil Velikov <[email protected]>
* egl/x11: Set version of swrastLoader to 2Boyan Ding2015-06-181-1/+1
| | | | | | | | | | which it actually implements instead of the newest version defined in dri_interface.h Cc: "10.5 10.6" <[email protected]> Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* vc4: Move tile state/alloc allocation into the kernel.Eric Anholt2015-06-179-101/+72
| | | | | | | This avoids a security issue where userspace could have written the tile state/tile alloc behind the GPU's back, and will apparently be necessary for fixing stability bugs (tile state buffers are missing some top bits for the tile alloc's address).
* vc4: Move RCL generation into the kernel.Eric Anholt2015-06-1711-676/+725
| | | | | There weren't that many variations of RCL generation, and this lets us skip all the in-kernel validation for what we generated.
* vc4: Add dumping of VC4_PACKET_TILE_BINNING_MODE_CONFIG.Eric Anholt2015-06-171-1/+32
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* vc4: Fix memory leak from simple_list conversion.Eric Anholt2015-06-171-3/+2
| | | | | I accidentally shadowed the outside declaration, so we always returned NULL even when we'd found something in the cache.
* vc4: Track the number of BOs allocated and their size.Eric Anholt2015-06-172-7/+100
| | | | This is useful for BO leak debugging.
* i965: Fix textureGrad with cube samplersIago Toral Quiroga2015-06-181-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can't use sampler messages with gradient information (like sample_g or sample_d) to deal with this scenario because according to the PRM: "The r coordinate and its gradients are required only for surface types that use the third coordinate. Usage of this message type on cube surfaces assumes that the u, v, and gradients have already been transformed onto the appropriate face, but still in [-1,+1] range. The r coordinate contains the faceid, and the r gradients are ignored by hardware." Instead, we should lower this to compute the LOD manually based on the gradients and use a different sample message that takes the computed LOD instead of the gradients. This is already being done in brw_lower_texture_gradients.cpp, but it is restricted to shadow samplers only, although there is a comment stating that we should probably do this also for samplerCube and samplerCubeArray. Because of this, both dEQP and Piglit test cases for textureGrad with cube maps currently fail. This patch does two things: 1) Activates the texturegrad lowering pass for all cube samplers. 2) Corrects the computation of the LOD value for cube samplers. I had to do 2) because for cube maps the calculations implemented in the lowering pass always compute a value of rho that is twice the value we want (so we get a LOD value one unit larger than we want). This only happens for cube map samplers (all kinds). I am not sure about why we need to do this, but I suspect that it is related to the fact that cube map coordinates, when transported to a specific face in the cube, are in the range [-1, 1] instead of [0, 1] so we probably need to divide the derivatives by 2 when we compute the LOD. Doing that would produce the same result as dividing the final rho computation by 2 (or removing a unit from the computed LOD, which is what we are doing here). Fixes the following piglit tests: bin/tex-miplevel-selection textureGrad Cube -auto -fbo bin/tex-miplevel-selection textureGrad CubeArray -auto -fbo bin/tex-miplevel-selection textureGrad CubeShadow -auto -fbo Fixes 10 dEQP tests in the following category: dEQP-GLES3.functional.shaders.texture_functions.texturegrad.*cube* Reviewed-by: Ben Widawsky <[email protected]>
* nvc0/ir: can't have a join on a load with an indirect sourceIlia Mirkin2015-06-171-1/+1
| | | | | | | | | | | Triggers an INVALID_OPCODE warning on GK208. Seems rare enough to not warrant verification on other chips. Fixes the new piglits: ubo_array_indexing/fs-nonuniform-control-flow.shader_test ubo_array_indexing/vs-nonuniform-control-flow.shader_test Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* docs: mark GL_ARB_framebuffer_no_attachments done for i965Kevin Rogovin2015-06-172-2/+3
| | | | | | | Mark GL_ARB_framebuffer_no_attachments as done for i965. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* i965: enable ARB_framebuffer_no_attachments for Gen7+Kevin Rogovin2015-06-172-0/+7
| | | | | | | Enable GL_ARB_framebuffer_no_attachments in i965 for Gen7 and higher. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* i965: execution of frag-shader when it has atomic bufferKevin Rogovin2015-06-172-0/+7
| | | | | | | | Ensure that the GPU spawns the fragment shader thread for those fragment shaders with atomic buffer access. Reviewed-by: Tapani Pälli <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* mesa: function for testing if current frag-shader has atomicsKevin Rogovin2015-06-171-1/+6
| | | | | | | | Add helper function that checks if current fragment shader active of gl_context has atomic buffer access. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* i965: Use _mesa_geometric_ functions appropriatelyKevin Rogovin2015-06-1716-34/+70
| | | | | | | | | | | | | | Change references to gl_framebuffer::Width, Height, MaxNumLayers and Visual::samples to use the _mesa_geometry_ convenience functions for those places where the geometry of the gl_framebuffer is needed (in contrast to the geometry of the intersection of the attachments of the gl_framebuffer). This patch is to pave the way to enable GL_ARB_framebuffer_no_attachments on Gen7 and higher in i965. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* mesa: helper function for scissor box of gl_framebufferKevin Rogovin2015-06-172-15/+35
| | | | | | | | | Add helper convenience function that intersects the scissor values against a passed bounding box. In addition, to avoid replicated code, make the function _mesa_scissor_bounding_box() use this new function. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* mesa: add helper functions for geometry of gl_framebufferKevin Rogovin2015-06-172-1/+35
| | | | | | | | | | Add convenience helper functions for fetching geometry of gl_framebuffer that return the geometry of the gl_framebuffer instead of the geometry of the buffers of the gl_framebuffer when then the gl_framebuffer has no attachments. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* PATCH 03/10] mesa: Complete ARB_framebuffer_no_attachments in Mesa coreKevin Rogovin2015-06-171-29/+182
| | | | | | | | | | Implement GL_ARB_framebuffer_no_attachments in Mesa core - changes to conditions for framebuffer completenss - implement set/get functions for framebuffers for new functions in GL_ARB_framebuffer_no_attachments Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* mesa: Constants and functions for ARB_framebuffer_no_attachmentsKevin Rogovin2015-06-179-3/+84
| | | | | | | | Define the enumeration constants, function entry points and glGet for the GL_ARB_framebuffer_no_attachments. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* mesa: Define infrastructure for ARB_framebuffer_no_attachmentsKevin Rogovin2015-06-174-5/+46
| | | | | | | | | Define the infrastructure for the extension GL_ARB_framebuffer_no_attachments: - extension table - additions to gl_framebuffer Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* vc4: Make sure that direct texture clamps have a minimum value of 0.Eric Anholt2015-06-162-25/+66
| | | | | | | I was thinking of the MIN opcode in terms of unsigned math, but it's signed, so if you used a negative array index, you could read before the UBO. Fixes segfaults under simulation in piglit array indexing tests with mprotect-based guard pages.
* vc4: Swap around which src we spill to ra31/rb31.Eric Anholt2015-06-161-4/+4
| | | | | | | | I wanted to assert that src1 came from a non-unspilled register in shader validation, and this easily gets us that. And, as a bonus: total instructions in shared programs: 93347 -> 92723 (-0.67%) instructions in affected programs: 60524 -> 59900 (-1.03%)
* vc4: R4 is not a valid register for clamped direct texturing.Eric Anholt2015-06-161-1/+1
| | | | | Our array only goes to R3, and R4 is a special case that shouldn't be used.
* vc4: Factor out the live clamp register getter.Eric Anholt2015-06-161-8/+24
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* vc4: Drop the unused "stride" field of surfaces.Eric Anholt2015-06-161-1/+0
| | | | We're always looking at the slice anyway, when we would have needed it.
* vc4: Handle refcounting the exec BO like we do in the kernel.Eric Anholt2015-06-164-10/+34
| | | | | This reduces the diff to the kernel, and will be useful when I make the kernel allocate more BOs as part of validation.
* vc4: Use VC4_SET/GET_FIELD for some RCL packets.Eric Anholt2015-06-164-77/+89
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* vc4: Make symbolic values for packet sizes.Eric Anholt2015-06-164-57/+86
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* vc4: Use symbolic values in texture ptype validation.Eric Anholt2015-06-161-10/+13
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* vc4: Move vc4_packet.h to the kernel/ directory, since it's also shared.Eric Anholt2015-06-164-3/+3
| | | | I want to notice discrepancies when I diff -u between Mesa and the kernel.
* i965/gen9: Disable Mip Tail for YF/YS tiled surfacesAnuj Phogat2015-06-162-2/+11
| | | | | | | | | | | | | | | Disabling miptails fixed the buffer corruption happening in FBO which use YF/YS tiled renderbuffer or texture as color attachment. Spec recommends disabling mip tails only for non-mip-mapped surfaces. But, without disabling miptails I couldn't get correct data out of mipmapped YF/YS tiled surface. We need better understanding of miptails before start using them. For now this patch helps move things forward. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9: Set vertical and horizontal surface alignmentsAnuj Phogat2015-06-161-6/+26
| | | | | | | | | | Patch sets the alignments for texture and renderbuffer surfaces. V3: Make changes inside horizontal_alignment() and vertical_alignment() (Topi) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use BRW_SURFACE_* in place of GL_TEXTURE_*Anuj Phogat2015-06-161-3/+3
| | | | | | | | Makes no functional changes in the code. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Rename use_linear_1d_layout() and make it globalAnuj Phogat2015-06-162-5/+9
| | | | | | | | | This function will be utilised in later patches. V2: Make both pointers constants (Topi) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Set tiled resource mode in surface stateAnuj Phogat2015-06-162-0/+27
| | | | | | | | This patch sets the tiled resource mode for texture and renderbuffer surfaces. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* egl/dri2: implement platform_surfacelessHaixia Shi2015-06-168-1/+199
| | | | | | | | | | | | | | | | | | The surfaceless platform is for off-screen rendering only. Render node support is required. Only consider the render nodes. Do not use normal nodes as they require auth hooks. v3: change platform_null to platform_surfaceless v4: make libdrm required for surfaceless v5: remove modified include guards with defined(HAVE_SURFACELESS_PLATFORM) v6: use O_CLOEXEC for drm fd Signed-off-by: Haixia Shi <[email protected]> Signed-off-by: Zach Reizner <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/vec4: Fix the source register for indexed samplersNeil Roberts2015-06-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously when setting up the sample instruction for an indirect sampler the vec4 backend was directly passing the pseudo opcode's src0. However vec4_visitor::visit(ir_texture *) doesn't set the texture operation's src0 -- it's left as BAD_FILE, which when translated into a brw_reg gives the null register. In brw_SAMPLE, gen6_resolve_implied_move() inserts a MOV from the inst->base_mrf and sets the src0 appropriately. The indirect sampler case did not have a call to gen6_resolve_implied_move(). The fs backend avoids this because the platforms that support dynamic indexing of samplers (IVB+) have been converted to not use the fake-MRF hack, and instead send from proper GRFs. This patch makes it call gen6_resolve_implied_move before setting up the indirect message. This is similar to what is done for constant sampler numbers in brw_SAMPLE. The Piglit tests for sampler array indexing didn't pick this up because they were using a texture with a solid colour so it didn't matter what texture coordinates were actually used. The tests have now been changed to be more thorough in this commit: http://cgit.freedesktop.org/piglit/commit/?id=4f9caf084eda7 With that patch the tests for gs and vs are currently failing on Ivybridge, but this patch fixes them. There are no other changes to a Piglit run on Ivybridge. On Skylake the gs tests were failing even without the Piglit patch because Skylake needs the source registers to work correctly in order to send a message header to select SIMD4x2 mode. (The explanation in the commit message is partially written by Matt Turner) Tested-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* st/mesa: improve assertions in vp/fp translationMarek Olšák2015-06-161-2/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: don't rebind constant buffers after every state change if GS is activeMarek Olšák2015-06-161-9/+3
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: generalize sso stage interleaving checkChris Forbes2015-06-161-17/+38
| | | | | | | | For tessellation. v2: cleanup by Marek Olšák Reviewed-by: Brian Paul <[email protected]>
* mesa: remove unused variables from gl_programMarek Olšák2015-06-161-2/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* glsl: add ir reader support for ir_barrierChris Forbes2015-06-161-0/+15
| | | | | | Picked from the tessellation branch. Reviewed-by: Brian Paul <[email protected]>
* glsl: print locations of variablesMarek Olšák2015-06-161-2/+6
| | | | Reviewed-by: Brian Paul <[email protected]>
* configure.ac: rename LLVM_VERSION_PATCH to avoid conflict with llvm-config.hMarek Olšák2015-06-161-1/+1
| | | | Reviewed-by: Tom Stellard <[email protected]>
* Revert "glsl: remove restriction on unsized arrays in GLSL ES 3.10"Timothy Arceri2015-06-161-9/+1
| | | | | | | | | | | | This reverts commit adee54f8269c5e9f4fde91d19f0e465afc8f14d8. Further down in the GLSL ES 3.10 spec it say: "If an array is declared as the last member of a shader storage block and the size is not specified at compile-time, it is sized at run-time. In all other cases, arrays are sized only at compile-time." Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* mesa: set override_version per api version overrideTapani Pälli2015-06-161-14/+24
| | | | | | | | | | | Before 9b5e92f get_gl_override was called only once, but now it is called for multiple APIs (GLES2, GL), version needs to be set always. Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90797 Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Martin Peres <[email protected]> Tested-by: Martin Peres <[email protected]>
* i965: Fix aligning to the block size in intel_miptree_copy_sliceNeil Roberts2015-06-161-2/+4
| | | | | | | | | | | | | | | | | | This function was trying to align the width and height to a multiple of the block size for compressed textures. It was using align_w/h as a shortcut to get the block size as up until Gen9 this always happens to match. However in Gen9+ the alignment values are expressed as multiples of the block size so in effect the alignment values are always 4 for compressed textures as that is the minimum value we can pick. This happened to work for most compressed formats because the block size is also 4, but for FXT1 this was breaking because it has a block width of 8. This fixes some Piglit tests testing FXT1 such as spec@3dfx_texture_compression_fxt1@fbo-generatemipmap-formats Reviewed-by: Nanley Chery <[email protected]>
* nv50,nvc0: clamp uniform size to 64kIlia Mirkin2015-06-152-4/+4
| | | | | | | | | | The state tracker will pass through requests from buggy applications which will have the buffer size larger than the max allowed (64k). Clamp the size to 64k so that we don't get errors when uploading the constbuf data. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nvc0/ir: fix collection of first uses for texture barrier insertionIlia Mirkin2015-06-151-5/+11
| | | | | | | | | | | | | One of the places we have to insert texbars is in situations where the result of the tex gets overwritten by a different instruction (e.g. in a conditional statement). However in some situations it can actually appear as though the original tex itself is an overwriting instruction. This can naturally never really happen, so just ignore the tex instruction when it comes up. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90347 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
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