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* vbo: update/add commentsBrian Paul2010-05-271-15/+62
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* mesa: Remove unnecessary headers.Vinson Lee2010-05-271-5/+0
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* egl: Return NULL if we fail to load a default driverKristian Høgsberg2010-05-271-1/+1
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* mesa: remove unused includesBrian Paul2010-05-261-2/+0
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* mesa: rewrite _mesa_get_handle() and add some commentsBrian Paul2010-05-261-6/+14
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* mesa: move GLSL uniform functions into new source fileBrian Paul2010-05-266-858/+957
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* st/mesa: Remove unnecessary headers.Vinson Lee2010-05-263-6/+0
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* Enable hardware mipmap generation for radeon.Will Dyson2010-05-261-3/+8
| | | | | | | Use _mesa_meta_GenerateMipmap. It is Fast Enough(tm). Signed-off-by: Maciej Cencora <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Fix image_matches_texture_obj() MaxLevel checkWill Dyson2010-05-261-4/+7
| | | | | | | | | When generating or uploading a new (higher) mipmap level for an image, we can need to allocate a miptree for a level greater than texObj->MaxLevel. Signed-off-by: Maciej Cencora <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Fallback to software render if there is no miptree for an imageWill Dyson2010-05-261-4/+4
| | | | | | | | This can happen when checking if a software fallback for a higher level operation (such as GenerateMipmap) is needed. Signed-off-by: Maciej Cencora <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r300g: decouple drawing code and two-sided stencil refvalue fallbackMarek Olšák2010-05-273-205/+154
| | | | | | It's now more separate from the rest of the driver and it can be disabled by commenting out just 1 line. Well, I couldn't make the previous version work with SW TCL reliably, that's the reason of this little rework.
* r300g/swtcl: handle large index count properlyMarek Olšák2010-05-261-23/+53
| | | | This fixes piglit/draw-elements.
* r300g/swtcl: force vertex prefetching for non-indexed primitivesMarek Olšák2010-05-263-6/+7
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* r300g/swtcl: move emitting AOS to prepare_for_renderingMarek Olšák2010-05-263-11/+14
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* r300g/swtcl: vbo transfer sanity checksMarek Olšák2010-05-261-0/+6
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* r300g: add get_cs_info winsys entrypoint, abandon check_csMarek Olšák2010-05-266-7/+27
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* r300g/swtcl: do not use u_upload_mgr and do not compute max_indexMarek Olšák2010-05-262-40/+45
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* r300g: remove unnecessary includesMarek Olšák2010-05-261-10/+0
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* i965: Add support for EXT_timer_query on Ironlake.Eric Anholt2010-05-263-24/+68
| | | | | | We could potentially do this on G45 as well, though the units are different. On 965, the timestamp is tied to hclk, which would make supporting it harder.
* intel: Handle decode of PIPE_CONTROL instructions.Eric Anholt2010-05-261-0/+27
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* i965: Move Gen6 debugging emit_mi_flush into the Gen6 block.Eric Anholt2010-05-261-2/+2
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* i965: Don't PIPE_CONTROL instruction cache flush.Eric Anholt2010-05-261-1/+0
| | | | | | | | | | | | This is a workaround for Ironlake errata. The emit_mi_flush is used for a few purposes: 1) Flushing write caches for RTT (including blit to texture) 2) Pipe fencing for sync objects 3) Spamming cache flushes to track down cache flush bugs Spamming cache flushes seems less important than following the docs, and we should probably do that with a different mechanism than the one for render cache flushes.
* i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.Eric Anholt2010-05-261-0/+7
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* gallivm: Remove unnecessary headers.Vinson Lee2010-05-261-2/+0
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* st/xorg: Remove unnecessary headers.Vinson Lee2010-05-262-2/+0
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* util: Remove unnecessary headers.Vinson Lee2010-05-261-2/+0
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* st/dri: Remove dri.c from SCons build.Vinson Lee2010-05-261-1/+0
| | | | | This was missed in commit f501230db3a94c9328b8e769d9c17b2c3792e19c. Fixes SCons build.
* Revert the 'make static' part of 962f92611216e304c95e7c089b38d58066236014Kristian Høgsberg2010-05-262-81/+307
| | | | | | | | The es1 and es2 dispath table initialization code is generated from the API XML files and we can't easily share the dispatch table code setup. Keep the _mesa_init_shader_dispatch() part of the patch, but roll back the static-ization of shader entrypoints so es1 and es2 dispatch initialization still works.
* r300g: fix fence referencingMarek Olšák2010-05-261-0/+1
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* mesa: move all vertex array functions into varray.cBrian Paul2010-05-254-273/+274
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* mesa: added _mesa_GetVertexAttribIiv / AttribIuiv()Brian Paul2010-05-252-54/+146
| | | | Refactor the code for all the glGetVertexAttrib() functions.
* mesa: added _mesa_VertexAttribIPointer()Brian Paul2010-05-252-0/+24
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* mesa: new GL 3.0 VertexAttrib commandsBrian Paul2010-05-251-0/+174
| | | | Still need to plug in API dispatch...
* mesa: make a bunch of shader API functions staticBrian Paul2010-05-253-377/+173
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* mesa: display list support for uint uniformsBrian Paul2010-05-251-1/+199
| | | | Still need to plug into dispatcher...
* mesa: consolidate some glUniform codeBrian Paul2010-05-251-78/+29
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* mesa: unsigned int uniform functions (GL3)Brian Paul2010-05-252-0/+96
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* mesa: support for unsigned int uniformsBrian Paul2010-05-251-1/+55
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* r300/compiler: implement SGT+SLE opcodesMarek Olšák2010-05-261-0/+20
| | | | Reported-by: Gianluca Anzolin <[email protected]>
* r300/compiler: fix dumping r5xx vertex shadersMarek Olšák2010-05-261-0/+3
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* r300/compiler: move hardware caps to the radeon_compiler base structMarek Olšák2010-05-268-20/+23
| | | | Needed for vertex shaders too.
* r300/compiler: shorten swizzle expressionsMarek Olšák2010-05-261-44/+65
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* rbug: add set sample mask passthrough.Dave Airlie2010-05-261-0/+12
| | | | | | This at least stops rbug segfaulting at startup. Signed-off-by: Dave Airlie <[email protected]>
* r300g: more efficient finish + fix commentsMarek Olšák2010-05-262-6/+7
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* r300g: implement fake but compliant fencesMarek Olšák2010-05-264-35/+63
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* r300g: add r300_init_render_functions, remove r300_render.hMarek Olšák2010-05-254-174/+84
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* r300g: remove r300_query.hMarek Olšák2010-05-254-38/+7
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* r300g: remove r300_flush.hMarek Olšák2010-05-254-30/+1
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* r300g: add r300_init_blit_functions, remove r300_blit.hMarek Olšák2010-05-254-77/+28
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* util: update comments at blitterMarek Olšák2010-05-251-1/+1
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