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* iris: add support for INTEL_conservative_rasterizationMike Blumenkrantz2019-04-233-11/+35
| | | | | | | | | this hooks up the iris gallium driver to existing mesa bits which handle the implementation resolves kwg/mesa#8 Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: indicate intel extension support for inner_coverage based on capMike Blumenkrantz2019-04-233-0/+4
| | | | | | | | if the driver (iris) indicates support for the inner_coverage pipe cap, this will set the necessary states in the driver flags and rasterizer structs Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: add pipe cap for inner_coverage conservative raster modeMike Blumenkrantz2019-04-233-0/+4
| | | | | | | this can be used by drivers which support the extension to indicate support Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Fix DrawTransformFeedback math when there's a buffer offsetKenneth Graunke2019-04-233-0/+14
| | | | | | | We need to subtract the starting offset from the final offset before dividing by the stride. See src/intel/vulkan/genX_cmd_buffer.c:3142. Not known to fix anything.
* iris: Make some offset math helpers take a const isl_surf pointerKenneth Graunke2019-04-231-2/+2
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* spirv: Handle SpvOpDecorateIdCaio Marcelo de Oliveira Filho2019-04-231-0/+4
| | | | | | | | | | | This operation decorate with an Id instead of a Literal or String. It is used by HlslCounterBufferGOOGLE (provided by SPV_GOOGLE_hlsl_functionality1). Even if we don't do anything with that decoration, we must be able to parse SPIR-V that uses it. Fixes: 891886da2f9 "spirv: Add no-op support for VK_GOOGLE_hlsl_functionality1" Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Rename vtn_decoration literals to operandsCaio Marcelo de Oliveira Filho2019-04-235-39/+39
| | | | | | | | Decorations (and ExecutionModes) can have not only literals, but also Ids associated with them. So rename the field to the more general name "Operand" used by the spec. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: fix argument name for vkCmdEndQueryLionel Landwerlin2019-04-241-2/+2
| | | | | | | | | | Doesn't fix anything but it's not the right function prototype. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 673f33c77dd765 ("anv: Implement CmdBegin/EndQueryIndexed") Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]>
* virgl: skip empty cmdbufsChia-I Wu2019-04-232-0/+9
| | | | | | | | Several empty cmdbufs are submitted by app/xserver per frame, from glamor_block_handler for example. Let's skip them. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* gallium: Remove the malloc pipebuffer manager.Eric Anholt2019-04-234-209/+0
| | | | | | | | This has been unused since r600 stopped using it in 2010. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* gallium: Remove the "alt" pipebuffer manager interface.Eric Anholt2019-04-234-127/+0
| | | | | | | | | This one would allocate from two underlying pools, but has never been used. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* gallium: Remove the ondemand pipebuffer manager.Eric Anholt2019-04-234-322/+0
| | | | | | | | I couldn't find any uses in the tree since its introduction. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* gallium: Remove the pool pipebuffer manager.Eric Anholt2019-04-234-342/+1
| | | | | | | | | Noticed while trying to decide if pipebuffer was of any use to me, and found that nothing has used it in the last 10 years at least. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* freedreno: a2xx: same gmem2mem sequence for all tilesJonathan Marek2019-04-231-12/+25
| | | | | | | | | | Set REG_A2XX_RB_COPY_DEST_OFFSET in the tile init as it won't get touched by the draw batch. Then gmem2mem is the same for all tiles. Similar to what is done in a6xx, but only for gmem2mem. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: enable batch reorderingJonathan Marek2019-04-231-3/+2
| | | | | | | Batch reordering on a2xx is now tested and functional. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: use nir_lower_io for TGSI shadersJonathan Marek2019-04-232-50/+11
| | | | | | | | | Allows removing the load_deref/store_deref code in the compiler. tgsi_to_nir now uses screen instead of options so we can simplify that too. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: disable PIPE_CAP_PACKED_UNIFORMSJonathan Marek2019-04-231-1/+3
| | | | | | | | | a2xx driver is currently broken when PIPE_CAP_PACKED_UNIFORMS is enabled, disable it for now. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: fix builtin blit program compilationJonathan Marek2019-04-231-0/+1
| | | | | | | | tgsi_to_nir now requires a screen pointer and is used by fd2_prog_init. fd2_prog_init is used before fd_context_init so set the pointer manually. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* svga: add new ATC formats to the format conversion tableJonathan Marek2019-04-231-0/+3
| | | | | | | Fixes the static assertion error. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno: a2xx: add GL_AMD_compressed_ATC_texture supportJonathan Marek2019-04-231-0/+6
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno: a3xx: add GL_AMD_compressed_ATC_texture supportJonathan Marek2019-04-231-0/+4
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* st/mesa: add ATC supportJonathan Marek2019-04-232-0/+19
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe, softpipe: no support for ATC texturesJonathan Marek2019-04-233-5/+8
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add ATC format supportJonathan Marek2019-04-235-3/+17
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: add GL_AMD_compressed_ATC_texture supportJonathan Marek2019-04-2312-2/+77
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: delay adding BOs at the beginning of IBs until the first drawMarek Olšák2019-04-236-9/+46
| | | | | | | so that bound compute shader resources won't be added when they are not needed and same for graphics. Acked-by: Nicolai Hähnle <[email protected]>
* radeonsi: add helper si_get_minimum_num_gfx_cs_dwordsMarek Olšák2019-04-232-7/+12
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* radeonsi: add si_cp_copy_dataMarek Olšák2019-04-235-41/+44
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: clean up and remove nonsensical assertionMarek Olšák2019-04-231-2/+1
| | | | | | | | The assertion considers max_dw from the current IB in the chain, but big_ib_buffer is a buffer for the next IB, which can be smaller. Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: enable chaining for compute IBsMarek Olšák2019-04-231-6/+6
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: reorder chunks, make BO_HANDLES first, IB and FENCE lastMarek Olšák2019-04-231-19/+17
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: make IBs writable and expose their addressMarek Olšák2019-04-232-1/+4
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* ac: add REWIND and GDS registers to register headersMarek Olšák2019-04-231-0/+16
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* ac: add ac_get_i1_sgpr_maskMarek Olšák2019-04-232-0/+18
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* ac: add radeon_info::is_pro_graphicsMarek Olšák2019-04-232-0/+5
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* ac: add radeon_info::marketing_name, replacing the winsys callbackMarek Olšák2019-04-236-33/+7
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: add uses_drawidMarek Olšák2019-04-233-0/+7
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* iris: Track valid data range and infer unsynchronized mappings.Kenneth Graunke2019-04-235-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | Applications frequently call glBufferSubData() to consecutive regions of a VBO to append new vertex data. If no data exists there yet, we can promote these to unsynchronized writes, even if the buffer is busy, since the GPU can't be doing anything useful with undefined content. This can avoid a bunch of unnecessary blitting on the GPU. u_threaded_context would do this for us, and in fact prohibits us from doing so (see TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED). But we haven't hooked that up yet, and it may be useful to disable u_threaded_context when debugging...at which point we'd still want this optimization. At the very least, it would let us measure the benefit of threading independently from this optimization. And it's not a lot of code. Removes most stall avoidance blits in "Total War: WARHAMMER." On my Skylake GT4e at 1920x1080, this appears to improve performance in games by the following (but I did not do many runs for proper statistics gathering): ---------------------------------------------- | DiRT Rally | +2% (avg) | + 2% (max) | | Bioshock Infinite | +3% (avg) | + 9% (max) | | Shadow of Mordor | +7% (avg) | +20% (max) | ----------------------------------------------
* iris: Make a resource_is_busy() helperKenneth Graunke2019-04-231-4/+13
| | | | This checks both "is it busy" and "do we have work queued up for it"?
* iris: Replace buffer backing storage and rebind to update addresses.Kenneth Graunke2019-04-234-5/+171
| | | | | | | | | | | | | | | | This implements PIPE_CAP_INVALIDATE_BUFFER and invalidate_resource(), as well as the PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE flag. When either of these happen, we swap out the backing storage of the buffer for a new idle BO, allowing us to write to it immediately without stalling or queueing a blit. On my Skylake GT4e at 1920x1080, this improves performance in games: ----------------------------------------------- | DiRT Rally | +25% (avg) | +17% (max) | | Bioshock Infinite | +22% (avg) | +11% (max) | | Shadow of Mordor | +27% (avg) | +83% (max) | -----------------------------------------------
* iris: Make memzone_for_address non-staticKenneth Graunke2019-04-232-5/+7
| | | | I want to use this in iris_resource.c.
* iris: Make a gl_shader_stage -> pipe_shader_stage helper functionKenneth Graunke2019-04-231-0/+14
| | | | | | This is probably not the best place for it, but I don't feel like moving the one out of the TGSI translator today, and we already have the other direction here, so...*shrug*
* iris: Rework image views to store pipe_image_view.Kenneth Graunke2019-04-234-35/+52
| | | | This will be useful when rebinding images.
* iris: Rework UBOs and SSBOs to use pipe_shader_bufferKenneth Graunke2019-04-232-104/+71
| | | | | | This unifies a bunch of the UBO and SSBO code to use common structures. Beyond iris_state_ref, pipe_shader_buffer also gives us a buffer size, which can be useful when filling out the surface state.
* iris: Track bound constant buffersKenneth Graunke2019-04-232-0/+6
| | | | | This helps avoid having to iterate over [0, PIPE_MAX_CONSTANT_BUFFERS) looking to see if any resources are bound.
* iris: Mark constants dirty on transfer unmap even if no flushes occurKenneth Graunke2019-04-231-2/+8
| | | | | | | | | | | | I have various conditions in place to try and avoid unnecessary PIPE_CONTROL flushes, especially to batches which may have never used the buffer being mapped. But if we do a CPU map to a bound constant buffer, we still need to mark push constants dirty, even if there's nothing happening in batches that would warrant a flush. Fixes obvious misrendering in the "XCOM 2: War of the Chosen" menus (lots of rainbow colored triangles). Fixes lots of blinking elements in "Shadow of Mordor". Fixes missing crowd rendering in "DiRT Rally".
* intel: workaround VS fixed function issue on Gen9 GT1 partsLionel Landwerlin2019-04-231-0/+12
| | | | | | | | | | | | The issue is noticeable in the dEQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_3d test where a triangle goes missing when we use the maximum number of URB entries as specified by the documentation. Signed-off-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107505 Reviewed-by: Kristian H. Kristensen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* intel/compiler: Improve fix_3src_operand()Matt Turner2019-04-221-5/+18
| | | | | | | | | | | | | | | | | | Allow ATTR and IMM sources unconditionally (ATTR are just GRFs, IMM will be handled by opt_combine_constants(). Both are already allowed by opt_copy_propagation(). Also allow FIXED_GRF if the regioning is 8,8,1. Could also allow other stride=1 regions (e.g., 4,4,1) and scalar regions but I don't think those occur. This is sufficient to allow a pass added in a future commit (fs_visitor::lower_linterp) to avoid emitting extra MOV instructions. I removed the 'src.stride > 1' case because it seems wrong: 3-src instructions on Gen6-9 are align16-only and can only do stride=1 or stride=0. A run through Jenkins with an assert(src.stride <= 1) never triggers, so it seems that it was dead code. Reviewed-by: Rafael Antognolli <[email protected]>
* intel/compiler: Add unit tests for sat prop for different exec sizesMatt Turner2019-04-221-0/+68
| | | | | | | The two new unit tests verify that propagating a saturate between instructions of different exec sizes does not happen. Reviewed-by: Rafael Antognolli <[email protected]>
* intel/compiler: Use SIMD16 instructions in fs saturate prop unit testMatt Turner2019-04-221-59/+59
| | | | | | | | | | | | Will allow us to test that propagation between instructions of different exec sizes does not happen (in the next commit). The stray-looking change in intervening_dest_write is to adjust the size of the texture result to keep the test functioning identically when the instructions' exec sizes are doubled. Without the change, the texture does not overwrite the destination fully as the unit test intends. Reviewed-by: Rafael Antognolli <[email protected]>
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