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* intel/compiler: lower some 16-bit integer operations to 32-bitIago Toral Quiroga2018-05-031-0/+21
| | | | | | | | | These are not supported in hardware for 16-bit integers. We do the lowering pass after the optimization loop to ensure that we lower ALU operations injected by algebraic optimizations too. Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/nir: add a lowering pass to convert the bit size of ALU operationsIago Toral Quiroga2018-05-034-0/+134
| | | | | | | | | | | | | | | | Not all bit-sizes may be supported natively in hardware for all operations. This pass allows drivers to lower such operations to a bit-size that is actually supported and then converts the result back to the original bit-size. Compiler backends control which operations and wich bit-sizes require the lowering through a callback function. v2: generalize this pass and make it available in NIR core (Rob, Jason) v3: remove some temporaries and reduce nesting in instruction loop using a continue statement (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: support negate and abs of half float immediatesJose Maria Casanova Crespo2018-05-031-2/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: fix brw_imm_w for negative 16-bit integersJose Maria Casanova Crespo2018-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | 16-bit immediates need to replicate the 16-bit immediate value in both words of the 32-bit value. This needs to be careful to avoid sign-extension, which the previous implementation was not handling properly. For example, with the previous implementation, storing the value -3 would generate imm.d = 0xfffffffd due to signed integer sign extension, which is not correct. Instead, we should cast to uint16_t, which gives us the correct result: imm.ud = 0xfffdfffd. We only had a couple of cases hitting this path in the driver until now, one with value -1, which would work since all bits are one in this case, and another with value -2 in brw_clip_tri(), which would hit the aforementioned issue (this case only affects gen4 although we are not aware of whether this was causing an actual bug somewhere). v2: Make explicit uint32_t casting for left shift (Jason Ekstrand) Reviewed-by: Jason Ekstrand <[email protected]> Cc: "18.0 18.1" <[email protected]>
* intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediateJose Maria Casanova Crespo2018-05-031-4/+8
| | | | | | | | | | | | | | | | | | | | | From Intel Skylake PRM, vol 07, "Immediate" section (page 768): "For a word, unsigned word, or half-float immediate data, software must replicate the same 16-bit immediate value to both the lower word and the high word of the 32-bit immediate field in a GEN instruction." This fixes the int16/uint16 negate and abs immediates that weren't taking into account the replication in lower and upper words. v2: Integer cases are different to Float cases. (Jason Ekstrand) Included reference to PRM (Jose Maria Casanova) v3: Make explicit uint32_t casting for left shift (Jason Ekstrand) Split half float implementation. (Jason Ekstrand) Fix brw_abs_immediate (Jose Maria Casanova) Cc: "18.0 18.1" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement nir_instr_type_load_const for 16-bit constantsJose Maria Casanova Crespo2018-05-031-0/+5
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement conversions from 16-bit int/float to boolIago Toral Quiroga2018-05-031-5/+11
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement conversion between float/int 16-bit typesIago Toral Quiroga2018-05-031-0/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compiler: handle conversion to smaller type in the lowering pass for thatIago Toral Quiroga2018-05-032-12/+7
| | | | | | | The lowering pass was specialized to act on 64-bit to 32-bit conversions only, but the implementation is valid for other cases. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: fix isign for 16-bit integersIago Toral Quiroga2018-05-031-5/+12
| | | | | | | | | | | | | We need to use 16-bit constants with 16-bit instructions, otherwise we get the following validation error: "Destination stride must be equal to the ratio of the sizes of the execution data type to the destination type" Because the execution data type is 4B due to the 32-bit integer constant. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Always try to create a logical contextChris Wilson2018-05-031-15/+14
| | | | | | | | | | | | | | | | | Always enable use of HW logical contexts to preserve GPU state between batches when the kernel supports such constructs, continuing to enforce the required support for gen6+. At runtime, this effectively removes the BRW_NEW_CONTEXT flag (and the upload of invariant state) from the start of every batch for any kernel supporting contexts. So long as the older atoms are correctly listening to the right flag (NEW_CONTEXT rather than NEW_BATCH) this should eliminate a few redundant state uploads for the older platforms. No piglits were harmed on ctg and ilk, both with and without logical contexts. Reviewed-by: Kenneth Graunke <[email protected]>
* spirv: Apply OriginUpperLeft to FragCoordNeil Roberts2018-05-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This behaviour was changed in 1e5b09f42f694687ac. The commit message for that says it is just a “tidy up” so my assumption is that the behaviour change was a mistake. It’s a little hard to decipher looking at the diff, but the previous code before that patch was: if (builtin == SpvBuiltInFragCoord || builtin == SpvBuiltInSamplePosition) nir_var->data.origin_upper_left = b->origin_upper_left; if (builtin == SpvBuiltInFragCoord) nir_var->data.pixel_center_integer = b->pixel_center_integer; After the patch the code was: case SpvBuiltInSamplePosition: nir_var->data.origin_upper_left = b->origin_upper_left; /* fallthrough */ case SpvBuiltInFragCoord: nir_var->data.pixel_center_integer = b->pixel_center_integer; break; Before the patch origin_upper_left affected both builtins and pixel_center_integer only affected FragCoord. After the patch origin_upper_left only affects SamplePosition and pixel_center_integer affects both variables. This patch tries to restore the previous behaviour by changing the code to: case SpvBuiltInFragCoord: nir_var->data.pixel_center_integer = b->pixel_center_integer; /* fallthrough */ case SpvBuiltInSamplePosition: nir_var->data.origin_upper_left = b->origin_upper_left; break; This change will be important for ARB_gl_spirv which is meant to support OriginLowerLeft. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Fixes: 1e5b09f42f694687ac "spirv: Tidy some repeated if checks..."
* spirv: convert some operands for bitwise shift and bitwise ops to uint32Samuel Iglesias Gonsálvez2018-05-031-0/+35
| | | | | | | | | | | | | | | | | SPIR-V allows to define the shift, offset and count operands for shift and bitfield opcodes with a bit-size different than 32 bits, but in NIR the opcodes have that limitation. As agreed in the mailing list, this patch adds a conversion to 32 bits to fix this. For more info, see: https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html v2: - src_bit_size will have zero value for variable bit-size operands (Jason). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: enable geom shaders in OpenGL 3.2 Compat profileTimothy Arceri2018-05-031-2/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radv: UseEnumerateInstanceVersion for the default version.Bas Nieuwenhuizen2018-05-021-1/+1
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Don't check the incoming apiVersion on CreateInstance.Bas Nieuwenhuizen2018-05-021-9/+0
| | | | | | | | | This fixes dEQP-VK.api.device_init.create_instance_invalid_api_version CC: 18.1 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Allow vkEnumerateInstanceVersion ProcAddr without instance.Bas Nieuwenhuizen2018-05-021-1/+1
| | | | | | | | | | | | Apparently the somewhere between 1.1.70 and 1.1.73 the loader started depending on this. The loader then creates a 1.0 instance, which gets into funny situation because we have a 1.1 device. No idea how to do line wrapping in Mako though, my random guesses did not work. CC: 18.1 <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: aubinator: add an option to limit the number of decoded VBO linesLionel Landwerlin2018-05-021-16/+23
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: limit to the number decoded lines from VBOLionel Landwerlin2018-05-023-8/+17
| | | | | | | | By default we set no limit, but the debug batch decoder in i965 sets it to 100. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Advertise variableMultisampleRateJason Ekstrand2018-05-021-1/+1
| | | | | | | | Initially, I didn't understand this feature. Turns out that all it means is that you can switch multisample rates in the middle of a zero-attachment subpass. We've been able to do this since forever. Reviewed-by: Anuj Phogat <[email protected]>
* nir: add missing dependency in meson.buildRob Clark2018-05-021-1/+1
| | | | | | | | | | nir_builder_opcodes.h also depends on nir_intrinsics.py for generating the system-value builders. Reported-by: Christoph Haag <[email protected]> Reported-by: Kenneth Graunke <[email protected]> Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radv: fix multisample image copiesMatthew Nicholls2018-05-022-110/+196
| | | | | | | | | | | | | | | | | | | Previously before fb077b0728, the LOD parameter was being used in place of the sample index, which would only copy the first sample to all samples in the destination image. After that multisample image copies wouldn't copy anything from my observations. This fixes some copy_and_blit CTS tests. v3.1: - set lod to 0 for nir_txf_ms (Samuel) v2: - use GLSL_SAMPLER_DIM_MS instead of 2D (Samuel) - updated commit description (Samuel) Fix this properly by copying each sample in a separate radv_CmdDraw and using a pipeline with the correct rasterizationSamples for the destination image. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* intel: Fix 3DSTATE_CONSTANT buffer decoding.Kenneth Graunke2018-05-021-15/+25
| | | | | | | | | | First, this was iterating over the 3DSTATE_CONSTANT_* instruction but trying to process fields of the 3DSTATE_CONSTANT_BODY substructure. Secondly, the fields have been called Buffer[0] and Read Length[0], for a while now, and we were not handling the subscripts correctly. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: fix aubinator includeLionel Landwerlin2018-05-021-1/+1
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 7c22c150c40b3 ("intel: Move batch decoder/disassembler from tools/ to common/") Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reuse batch decoder infrastructure rather than open coding it.Kenneth Graunke2018-05-023-223/+55
| | | | | | | | | With the new callback, Jason's newer batch decoder infrastructure should be able to do just as well as the old open coded INTEL_DEBUG=bat handling, with much less code. If there are any limitations, we'd like to improve the common code rather than doing one-off hacks here. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Give the batch decoder a callback to ask about state size.Kenneth Graunke2018-05-024-6/+28
| | | | | | | | | Given an arbitrary batch, we don't always know what the size of certain things are, such as how many entries are in a binding table. But it's easy for the driver to track that information, so with a simple callback we can calculate this correctly for INTEL_DEBUG=bat. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Move batch decoder/disassembler from tools/ to common/Kenneth Graunke2018-05-027-11/+9
| | | | | | | | Making these part of libintel_common allows us to use them in the DRI driver. The standalone tool binaries already link against the common library, too, so it's no harder for them. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Allocate shadow batches to explicitly be the BO size.Kenneth Graunke2018-05-021-7/+5
| | | | | | | | | | | | | | This unfortunately makes it malloc/realloc on every new batch, rather than once at startup. But it ensures that the shadow buffer's size will absolutely match the BO size. Otherwise, as we tune BATCH_SZ/STATE_SZ or bufmgr cache bucket sizes, we may get a BO size that's rounded up, and fail to allocate the shadow buffer large enough. This doesn't fix any bugs today, as BATCH_SZ/STATE_SZ are the size of a cache bucket, but it's better to be safe than sorry. Reported-by: James Xiong <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: batch-decoder: iterate VERTEX_BUFFER_STATE fieldsLionel Landwerlin2018-05-021-31/+39
| | | | | | | | | The gen_field_iterator only iterates the fields of a given gen_group. If we want to iterate the fields of another gen_group contained as field, we need to do it manually. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: fix starting dword of struct fieldsLionel Landwerlin2018-05-021-2/+3
| | | | | | | | | | | | Struct fields might span several dwords, but iter_dword is incremented up to the last dword of the current field before we print out the struct's fields. We can't use iter_dword for computing the offset into the pointer of data to decode. v2: Fix displayed offset number (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: document when fields should be usedLionel Landwerlin2018-05-021-3/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: identify groups with fixed lengthLionel Landwerlin2018-05-022-6/+13
| | | | | | | | | | | | | | <register> & <struct> elements always have fixed length. The get_length() method implies that we're dealing with an instruction in which the length is encoded into the variable data but the field iterator uses it without checking what kind of gen_group it is dealing with. Let's make get_length() report the correct length regardless of the gen_group (register, struct or instruction). Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: make the field iterator use more naturalLionel Landwerlin2018-05-022-30/+36
| | | | | | | | | | | while (iter_next()) { ... } instead of do { ... } while (iter_next()); Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nv50: Extract needed value bits without shifting them before calling bitcountVlad Golovkin2018-05-021-1/+1
| | | | | | | This can save one instruction since bitcount doesn't care about specific bits' positions. Reviewed-by: Karol Herbst <[email protected]>
* intel: activate the gl_BaseVertex loweringAntia Puentes2018-05-028-27/+11
| | | | | | | | | | | | | | | | | | | | | | | | | Surplus code related to the basevertex is removed. The Vertex Elements contain now: * VE 1: <firstvertex, BaseInstance, VertexID, InstanceID> * VE 2: <DrawID, is_indexed_draw, 0, 0> Also fixes unreachable message. Fixes OpenGL CTS tests: * KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters * KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters * KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters * KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysParameters * KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters Fixes Piglit tests: * arb_shader_draw_parameters-drawid-indirect baseinstance * arb_shader_draw_parameters-basevertex Reviewed-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
* compiler/nir: Add conditional lowering for gl_BaseVertexAntia Puentes2018-05-022-0/+21
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel: emit is_indexed_draw in the same VE than gl_DrawIDAntia Puentes2018-05-027-48/+78
| | | | | | | | | | | The Vertex Elements are now: * VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID> * VE 2: <DrawID, is-indexed-draw, 0, 0> VE1 is it kept as it was before, VE2 additionally contains the new system value. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Add uses_is_indexed_draw flagAntia Puentes2018-05-022-0/+5
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* compiler: Add SYSTEM_VALUE_IS_INDEXED_DRAW and instrinsicsAntia Puentes2018-05-025-0/+14
| | | | | | | | | This VS system value contains if the draw command used to start the rendering was an indexed draw command or a non-indexed one (~0/0 respectively). Useful to calculate the gl_BaseVertex as: (SYSTEM_VALUE_IS_INDEXED_DRAW & SYSTEM_VALUE_FIRST_VERTEX). Reviewed-by: Jason Ekstrand <[email protected]>
* radv: enable out-of-order rasterization by defaultSamuel Pitoiset2018-05-022-2/+3
| | | | | | | | | | | As the implementation is conservative, we can now enable it by default. It can be disabled with RADV_DEBUG=nooutoforder. Don't expect much more than 1% of improvements, but the gain seems consistent. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: only disable out-of-order rast for perfect occlusion queriesSamuel Pitoiset2018-05-022-10/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: Drop unused gen5 sampler default color struct.Kenneth Graunke2018-05-011-9/+0
| | | | Trivial.
* i965: Make brw_vs_outputs_written static.Kenneth Graunke2018-05-012-5/+1
| | | | Drop a prototype. Trivial.
* i965/tex_image: Avoid the ASTC LDR workaround on gen9lpNanley Chery2018-05-011-1/+1
| | | | | | | | | | | Both the internal documentation and the results of testing this in the CI suggest that this is unnecessary. Add the fixes tag because this reduces an internal benchmark's startup time by about 17 seconds (reported by Eero). Fixes: 710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values" Tested-by: Eero Tamminen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* freedreno: Fix ir3_cmdline.c build.Eric Anholt2018-05-011-0/+1
| | | | | | Fixes: 6487e7a30c9e ("nir: move GL specific passes to src/compiler/glsl") Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* anv: Allow lookup of vkEnumerateInstanceVersion without an instanceJason Ekstrand2018-05-011-0/+1
| | | | | Fixes: cbab2d1da5edfe9df27a010adf8b1aa9dbee473b Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv: Don't advertise Float64 or Int64 on HW without 64-bit typesJason Ekstrand2018-05-011-2/+4
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* radv: compute the number of subpass attachments correctlySamuel Pitoiset2018-05-011-2/+2
| | | | | | | | | Only count color attachments twice if resolves are used, also account for the depth stencil attachment if present. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]>
* radv: set fmask_surf_index on fmask surfaces.Dave Airlie2018-05-021-1/+3
| | | | | | | | | This is needed for gfx9 and later for all fmask surface index. (Mentioned by Marek on irc) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/i915: fix PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE typoBrian Paul2018-05-011-1/+1
| | | | | | Fixes: fffe5e2d14f807c ("gallium: add initial support for conservative rasterization") Trivial.
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