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* radv/gfx10: always build the GS copy shader but uses it on-demandSamuel Pitoiset2019-07-173-7/+24
| | | | | | | | | It should be possible to build it on-demand too but it requires more work. On GFX10, the GS copy shader is required when tess is enabled with extreme geometry. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* softpipe: Remove unused static functionGert Wollny2019-07-171-9/+0
| | | | | | | | | | | Thanks to Eric Engestrom for pointing out that there was something wrong with that function. Fixes: 724a73509e1bc1ce3abf9500e457bb2911b642db softpipe: Prepare handling explicit gradients Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* spirv: Bail when we see CounterBuffer decorationCaio Marcelo de Oliveira Filho2019-07-161-1/+1
| | | | | | | This decoration can be ignored, so we can just skip the next steps. Otherwise we'd have to also handle it in apply_var_decoration. Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Drop copy and pasted iris_timebase_scaleKenneth Graunke2019-07-163-12/+3
| | | | | Lionel moved brw_timebase_scale to gen_device_info_timebase_scale a few months ago, so we should just use that, and not our own copy in iris.
* nir/regs_to_ssa: Handle regs in phi sources properlyJason Ekstrand2019-07-161-2/+32
| | | | | | | | | | | | | Sources of phi instructions act as if they occur at the very end of the predecessor block not the block in which the phi lives. In order to handle them correctly, we have to skip phi sources on the normal instruction walk and handle them as a separate walk over the successor phis. While registers in phi instructions is a bit of an oddity it can happen when we temporarily go out-of-SSA for control-flow manipulations. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111075 Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: Add a warning for ArrayStride on arrays of blocksJason Ekstrand2019-07-161-2/+9
| | | | | | | | | | | It's disallowed according to the SPIR-V spec or at least I think that's what the spec says. It's in a section explicitly about explicit layout of things in the StorageBuffer, Uniform, and PushConstant storage classes so it's not 100% clear that it applies with other storage classes. However, it seems like it should apply in general and violating it can trigger (fairly harmless) asserts in NIR. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv: Increase state allocation size limit to 2MBCaio Marcelo de Oliveira Filho2019-07-161-1/+1
| | | | | | | | When running on ICL the dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13 needs more than 1M for the shader, so bump it. Reviewed-by: Jason Ekstrand <[email protected]>
* meta: leaking of BO with DrawPixelsYevhenii Kolesnikov2019-07-161-0/+2
| | | | | | | | | | ctx->Unpack.BufferObj wasn't unreferenced. Fixes: d492e7b0171 (meta: Fix invalid PBO access from DrawPixels when trying to just alloc.) CC: Eric Anholt <[email protected]> Signed-off-by: Yevhenii Kolesnikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* swrast: Move _mesa_format_pack_colormask() to the only caller.Eric Anholt2019-07-163-78/+72
| | | | | | | | | This avoids needing format_pack to have access to the GLenum return functions for mesa_format. It seems like an odd function and unlikely to be reused. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* mesa: Give _mesa_format_get_color_encoding a clearer name.Eric Anholt2019-07-1614-35/+22
| | | | | | | It only returned one of two values. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* mesa: Drop redundant checks for sRGB before sRGB to linear conversion.Eric Anholt2019-07-162-6/+4
| | | | | | | | _mesa_get_srgb_format_linear() just returns the original format if it wasn't sRGB. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* mesa: Fold _mesa_unpack_depth_stencil_row() into its only caller.Eric Anholt2019-07-163-34/+14
| | | | | | | This was the last bit of gl.h usage in format packing. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* mesa: Convert format_pack/unpack off of GL types.Eric Anholt2019-07-164-353/+352
| | | | | Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* mesa: Port format_pack/unpack off of _mesa_problem().Eric Anholt2019-07-162-47/+17
| | | | | | | unreachable() should be plenty of debug for these. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* mesa: Mostly switch Mesa format info off of GL types other than GLenum.Eric Anholt2019-07-162-142/+144
| | | | | | | | I'm considering moving most of this code to src/util/, and I want that code to not expose GL types in its interfaces. Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* mesa: Rename gl_pack typedefs to mesa_pack.Eric Anholt2019-07-165-20/+20
| | | | | | | These are packing mesa formats, not a GL format/type. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* mesa: Rename gl_format_info to mesa_format_info.Eric Anholt2019-07-162-29/+29
| | | | | | | It's about MESA_FORMATs, after all. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* state_tracker: Move the format test out to be an actual unit test.Eric Anholt2019-07-163-51/+117
| | | | | | | | We want errors in the table to show up as unit test failures in MRs. Also keeps unit test code out of the built drivers. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* u_format: Remove pointless comments.Eric Anholt2019-07-161-6/+0
| | | | | Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* src/util: Switch _mesa_half_to_float() to u_half.h's version.Eric Anholt2019-07-161-43/+2
| | | | | | | | | The two implementations differ across the entire input range only in that u_half.h preserves mantissa bits for NaNs. The u_half.h version shaves 15% off of the text size of half_float.o. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* u_half_test: Turn it into an actual unit test.Eric Anholt2019-07-161-4/+5
| | | | | | | | You could break the test and meson test wouldn't complain, since we returned success either way. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* android: radv/gfx10: generate gfx10_format_table.hMauro Rossi2019-07-162-1/+17
| | | | | | | | | | | | | | | | | | | | | | This patch adds the missing building rules for Android, to avoid following building errors: In file included from external/mesa/src/amd/vulkan/radv_debug.c:35: In file included from external/mesa/src/amd/vulkan/radv_debug.h:27: external/mesa/src/amd/vulkan/radv_private.h:95:10: fatal error: 'gfx10_format_table.h' file not found ^~~~~~~~~~~~~~~~~~~~~~ 1 error generated. In file included from external/mesa/src/amd/vulkan/radv_android.c:31: external/mesa/src/amd/vulkan/radv_private.h:95:10: fatal error: 'gfx10_format_table.h' file not found ^~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Fixes: 3dc5ec5d16 ("radv/gfx10: generate gfx10_format_table.h") Signed-off-by: Mauro Rossi <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* mesa/st: add sampler uniformsRob Clark2019-07-161-6/+45
| | | | | | | | | | | Add sampler uniforms for the UV plane(s), so driver can count the uniforms and get the correct sampler count. Fixes lowered YUV on a6xx which actually wants to know # of samplers. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* egl/android: handle multi-fd native windowsRob Clark2019-07-161-25/+55
| | | | | | | | | | | | | | We can hit multi-fd EGL_NATIVE_BUFFER_ANDROID case when the native android buffer is YUV. So we need to handle that. Currently this went unnoticed because, even though we have two or three fd's for YUV native android buffers, they all reference the same backing buffer. But we really shouldn't rely on that. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st,i965: Stop looping on 64-bit loweringJason Ekstrand2019-07-163-30/+13
| | | | | | | | | Now that the 64-bit lowering passes do a complete lowering in one go, we don't need to loop anymore. We do, however, have to ensure that int64 lowering happens after double lowering because double lowering can produce int64 ops. Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_doubles: Handle fdiv and fsub directlyJason Ekstrand2019-07-162-2/+17
| | | | Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_doubles: Use the new NIR lowering frameworkJason Ekstrand2019-07-161-72/+65
| | | | | | | One advantage of this is that we no longer need to run in a loop because the new framework handles lowering instructions added by lowering. Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_doubles: Use "alu" for the nir_alu_instrJason Ekstrand2019-07-161-15/+15
| | | | Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_int64: Use the core NIR lowering frameworkJason Ekstrand2019-07-161-74/+49
| | | | | | | One advantage of this is that we no longer need to run in a loop because the new framework handles lowering instructions added by lowering. Reviewed-by: Eric Anholt <[email protected]>
* nir/alu_to_scalar: Use the new NIR lowering frameworkJason Ekstrand2019-07-161-93/+54
| | | | Reviewed-by: Eric Anholt <[email protected]>
* nir/alu_to_scalar: Use "alu" as the name for the nir_alu_instrJason Ekstrand2019-07-161-50/+50
| | | | Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_system_values: Support lowering more intrinsicsJason Ekstrand2019-07-161-87/+83
| | | | | | | | | | Instead of only lowering system from variables, lower most to intrinsics and let the lowering framework immediately lower the intrinsic. This will result in a bit more instruction churn but it means that NIR code builders can just use intrinsics instead of everything having to go through variables. Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_system_values: Drop the context-aware builder functionsJason Ekstrand2019-07-161-97/+96
| | | | | | | | | | Instead of having context-aware builder functions, just provide lowering for the system value intrinsics and let nir_shader_lower_instructions handle the recursion for us. This makes everything a bit simpler and means that the lowering can also be used if something comes in as a system value intrinsic rather than a load_deref. Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_system_values: Use the new generic NIR lowering helpersJason Ekstrand2019-07-161-96/+55
| | | | Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_subgroups: Use the new generic NIR lowering helpersJason Ekstrand2019-07-161-45/+14
| | | | Reviewed-by: Eric Anholt <[email protected]>
* nir: Add some generic helpers for writing lowering passesJason Ekstrand2019-07-162-0/+192
| | | | Reviewed-by: Eric Anholt <[email protected]>
* nir: Add a helper for fetching the SSA def from an instructionJason Ekstrand2019-07-162-0/+49
| | | | Reviewed-by: Eric Anholt <[email protected]>
* pandecode: Add more addresses to traceTomeu Vizoso2019-07-161-5/+5
| | | | | | | When debugging, we're given the fault_pointer unresolved, so it is helpful to have more context in the decode. Signed-off-by: Tomeu Vizoso <[email protected]>
* panfrost: Use 64-bit descriptors globallyTomeu Vizoso2019-07-165-67/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Midgard supports two modes of operation, 32-bit mode and 64-bit mode. The GPU is natively 64-bit, but job descriptors can be submitted in 32-bit mode. Among other changes, 32-bit mode shortens pointer sizes to use 32-bit pointers rather than the full 64-bit range. The blob decides which mode to use based on the CPU bitness, so an armhf system uses 32-bit descriptors and an aarch64 system uses 64-bit descriptors. For a while, we mimicked this, bu inevitably this caused the 32-bit support to lag behind as our reference platform is 64-bit. To combat the code staleness, we traced an older GPU paired with a 64-bit CPU (the Midgard T720 on-board the sunxi H64). From there, we could tell which fields were really about hardware and which fields were simply reflections of the descriptor bitness. From there, we decided to remove support for 32-bit descriptors entirely, using 64-bit descriptors unconditionally. There is minimal performance penalty for this in practice, and it allows us to unify these disparate code paths. This fixes: - T860 + armhf - T820 + armhf - T760 + aarch64 And will help bringup of 1st/2nd generation Midgard regardless of CPU. [Work done by Tomeu. Commit message written by Alyssa.] v2: Add comments preserving information about the old behaviour for future reference. Fix a compiler warning. (Alyssa) Signed-off-by: Alyssa Rosenzweig <[email protected]>
* anv: Account for dynamic stencil write disables in the PMA fixJason Ekstrand2019-07-161-0/+2
| | | | | | | | | | | In 6ce8592836b8 we started looking at the dynamic stencil state and disabling stencil writes when the stencil mask is zero. Unfortunately, we never updated the PMA fix code accordingly so 3DSTATE_WM_DEPTH_STENCIL and the PMA fix were getting out-of-sync causing hangs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109203 Fixes: 6ce8592836 "anv: Disable stencil writes when both write..." Reviewed-by: Lionel Landwerlin <[email protected]>
* panfrost: Implement opportunistic AFBCAlyssa Rosenzweig2019-07-165-1/+100
| | | | | | | | | | | | | | | | Rather than hardcoding a BO layout at creation-time, we implement the ability to hint layouts at various points in a BO's lifetime, potentially reallocating and switching layouts if it's heuristically deemed useful to do so. In this patch, we add a simple hinting implementation, opportunistically compressing FBOs. Support is hidden behind PAN_MESA_DEBUG=afbc as the implementation is incomplete (software access to AFBC is unimplemented at the moment) and therefore would regress significantly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/mfbd: Zero out framebuffer_strideAlyssa Rosenzweig2019-07-161-2/+3
| | | | | | We don't know what this is, so let's not pretend we do. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: AFBC buffers must be cache-line alignedAlyssa Rosenzweig2019-07-161-0/+5
| | | | | | Fixes a DATA_INVALID_FAULT when AFBC is paried with mipmapping. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add Z/S and MRT BOs to the jobAlyssa Rosenzweig2019-07-162-10/+12
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Set usage2 during draw, not CSOAlyssa Rosenzweig2019-07-162-24/+37
| | | | | | It can change from a layout switch. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* meta: memory leak of CopyPixels usageSergii Romantsov2019-07-161-0/+14
| | | | | | | | | Meta of CopyPixel generates a buffer object but does not free it on cleanup. Fixes: 37d11b13ce1d (meta: Don't pollute the buffer object namespace in _mesa_meta_setup_vertex_objects) Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radv: add radv_emit_streamout_{begin,end} helpersSamuel Pitoiset2019-07-161-8/+35
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: pass output values to radv_emit_stream_output()Samuel Pitoiset2019-07-161-13/+18
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: allow to select DST_SEL with RELEASE_MEMSamuel Pitoiset2019-07-164-3/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: allow to emit PS_DONE/CS_DONE with RELEASE_MEMSamuel Pitoiset2019-07-161-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
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