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* intel/fs: Don't use automatic exec size inferenceJason Ekstrand2017-11-071-3/+9
* intel/fs: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-074-9/+15
* intel/eu: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-071-0/+9
* intel/eu: Make automatic exec sizes a configurable optionJason Ekstrand2017-11-073-14/+29
* intel/fs: Rework zero-length URB write handlingJason Ekstrand2017-11-071-29/+31
* intel/compiler/fs: Set up subgroup invocation as a system valueJason Ekstrand2017-11-071-13/+21
* intel/cs: Push subgroup ID instead of base thread IDJason Ekstrand2017-11-079-36/+40
* intel/cs: Re-run final NIR optimizations for each SIMD sizeJason Ekstrand2017-11-071-41/+69
* intel/compiler: Move the destructor from vec4_visitor to backend_shaderJason Ekstrand2017-11-074-5/+5
* i965/fs: Get rid of the early return in brw_compile_csJason Ekstrand2017-11-071-13/+14
* intel/cs: Rework the way thread local ID is handledJason Ekstrand2017-11-076-46/+32
* intel/fs: Mark 64-bit values as being contiguousJason Ekstrand2017-11-071-1/+4
* intel/cs: Ignore runtime_check_aads_emit for CSJason Ekstrand2017-11-071-2/+1
* intel/cs: Stop setting dispatch_grf_start_regJason Ekstrand2017-11-072-3/+0
* intel/cs: Drop max_dispatch_width checks from compile_csJason Ekstrand2017-11-071-4/+8
* intel/fs: Remove min_dispatch_width from fs_visitorJason Ekstrand2017-11-073-33/+25
* intel/fs: use pull constant locations to check for first compile of a shaderJason Ekstrand2017-11-072-2/+7
* intel/fs: Retype dest to match value in read[First]InvocationJason Ekstrand2017-11-071-4/+2
* intel/fs: Uniformize the index in readInvocationJason Ekstrand2017-11-071-1/+1
* intel/fs: Protect opt_algebraic from OOB BROADCAST indicesJason Ekstrand2017-11-071-2/+11
* i965/fs/nir: Don't stomp 64-bit values to D in get_nir_srcJason Ekstrand2017-11-071-13/+24
* i965/fs/nir: Minor refactor of store_outputJason Ekstrand2017-11-071-4/+3
* i965/fs: Return a fs_reg from shuffle_64bit_data_for_32bit_writeJason Ekstrand2017-11-072-29/+12
* i965/fs/nir: Simplify 64-bit store_outputJason Ekstrand2017-11-071-19/+6
* intel/fs: Use the original destination region for int MUL loweringJason Ekstrand2017-11-071-7/+9
* intel/fs: Fix integer multiplication lowering for src/dst hazardsJason Ekstrand2017-11-071-2/+8
* intel/fs: Fix MOV_INDIRECT for 64-bit values on little-coreJason Ekstrand2017-11-071-36/+39
* intel/eu: Fix broadcast instruction for 64-bit values on little-coreJason Ekstrand2017-11-071-2/+24
* intel/eu/reg: Add a subscript() helperJason Ekstrand2017-11-071-0/+16
* intel/eu: Just modify the offset in brw_broadcastJason Ekstrand2017-11-071-4/+5
* intel/compiler: Add some restrictions to MOV_INDIRECT and BROADCASTJason Ekstrand2017-11-073-0/+20
* intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/allJason Ekstrand2017-11-071-9/+33
* intel/fs: Use an explicit D type for vote any/all/eq intrinsicsJason Ekstrand2017-11-071-0/+6
* intel/fs: Don't stomp f0.1 in SIMD16 ballotJason Ekstrand2017-11-071-2/+9
* intel/fs: Use ANY/ALL32 predicates in SIMD32Jason Ekstrand2017-11-071-12/+30
* intel/fs: Be more explicit about our placement of [un]zipJason Ekstrand2017-11-071-3/+17
* intel/fs: Pass builders instead of blocks into emit_[un]zipJason Ekstrand2017-11-071-26/+35
* intel/fs: Use a pure vertical stride for large register stridesJason Ekstrand2017-11-071-3/+13
* broadcom/vc5: Skip emitting textures that aren't used.Eric Anholt2017-11-071-2/+4
* broadcom/vc5: Add missing SRGBA8 ETC2 support.Eric Anholt2017-11-071-0/+1
* broadcom/vc5: Disable early Z test when the FS writes Z.Eric Anholt2017-11-071-1/+2
* broadcom/vc5: Shift the min/max lod fields by the BASE_LEVEL.Eric Anholt2017-11-072-4/+15
* broadcom/vc5: Add support for anisotropic filtering.Eric Anholt2017-11-071-0/+9
* broadcom/vc5: Fix mipmap filtering enums.Eric Anholt2017-11-072-8/+32
* broadcom/vc5: Fix height padding of small UIF slices.Eric Anholt2017-11-071-1/+5
* broadcom/vc5: Print the actual offsets in HW for our resource layout debug.Eric Anholt2017-11-071-34/+55
* broadcom/vc5: Set the available VS outputs to match the FS inputs.Eric Anholt2017-11-071-1/+4
* broadcom/vc5: Set the max texture LOD bias.Eric Anholt2017-11-071-1/+1
* broadcom/vc5: Fix translation of stencil ops.Eric Anholt2017-11-072-8/+30
* broadcom/vc5: Move stencil state packing to the CSO.Eric Anholt2017-11-073-27/+47
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