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* v3d: Add support for using the TFU to do some blits.Eric Anholt2018-12-141-42/+129
* v3d: Don't forget to bump the number of writes when doing TFU ops.Eric Anholt2018-12-141-0/+2
* v3d: Set up the right stride for raster TFU.Eric Anholt2018-12-141-1/+1
* v3d: Don't forget to wait for our TFU job before rendering from it.Eric Anholt2018-12-141-0/+8
* nvc0: always keep TSC slot 0 bound to fix TXFIlia Mirkin2018-12-142-0/+21
* nvc0: replace use of explicit default_tsc with entry 0Ilia Mirkin2018-12-146-22/+25
* freedreno/a6xx: fix corrupted uniformsRob Clark2018-12-141-1/+2
* pci_ids: add new vega20 pci idAlex Deucher2018-12-141-0/+1
* pci_ids: add new vega10 pci idsAlex Deucher2018-12-141-1/+7
* i965/gen9: Add workarounds for object preemption.Rafael Antognolli2018-12-141-0/+63
* i965/gen10+: Enable object level preemption.Rafael Antognolli2018-12-144-1/+36
* intel/genxml: Add register for object preemption.Rafael Antognolli2018-12-143-0/+24
* util/slab: Rename slab_mempool typed parameters to mempoolIan Romanick2018-12-142-14/+14
* nir/phi_builder: Internal users should use nir_phi_builder_value_set_block_de...Ian Romanick2018-12-141-2/+2
* etnaviv: drop redundant ctx function parameterChristian Gmeiner2018-12-141-4/+3
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-1416-260/+177
* nir: fix opt_if_loop_last_continue()Timothy Arceri2018-12-141-2/+6
* freedreno/a6xx: fix resource_copy_region()Rob Clark2018-12-131-9/+24
* freedreno: move fd_resource_copy_region()Rob Clark2018-12-133-62/+73
* freedreno/a6xx: more blitter fixesRob Clark2018-12-131-10/+22
* freedreno: update generated headersRob Clark2018-12-138-30/+39
* gallium/aux: add is_unorm() helperRob Clark2018-12-132-0/+24
* freedreno/a6xx: fix blitter crashRob Clark2018-12-131-0/+17
* freedreno/ir3: don't remove unused input componentsRob Clark2018-12-131-1/+7
* freedreno/ir3: fix crashRob Clark2018-12-131-14/+8
* freedreno: also set DUMP flag on shadersRob Clark2018-12-135-20/+22
* freedreno: debug GEM obj namesRob Clark2018-12-1313-21/+91
* freedreno/drm: sync uapi and enable softpinRob Clark2018-12-136-25/+30
* nir: Move intel's half-float image store lowering to to nir_format.h.Eric Anholt2018-12-132-8/+15
* Revert "intel: Simplify the half-float packing in image load/store lowering."Eric Anholt2018-12-131-2/+8
* nir: Print the format of image variables.Eric Anholt2018-12-131-0/+47
* mesa/st: Expose compute shaders when NIR support is advertised.Eric Anholt2018-12-132-8/+14
* radv/xfb: fix counter buffer bounds checks.Dave Airlie2018-12-131-2/+2
* i965: Enable nir_opt_idiv_const for 32 and 64-bit integersJason Ekstrand2018-12-131-1/+3
* i965/vec4: Implement nir_op_uadd_satJason Ekstrand2018-12-131-0/+6
* i965/fs: Implement nir_op_uadd_satIan Romanick2018-12-131-0/+5
* nir: Add a pass for lowering integer division by constantsJason Ekstrand2018-12-134-0/+219
* nir: Add a saturated unsigned integer add opcodeIan Romanick2018-12-131-0/+2
* nir/lower_int64: Add support for [iu]mul_highJason Ekstrand2018-12-132-0/+67
* nir: Allow [iu]mul_high on non-32-bit typesJason Ekstrand2018-12-132-4/+40
* glx: mandate xf86vidmode only for "drm" dri platformsEmil Velikov2018-12-133-6/+8
* nir: remove unused variableAlejandro Piñeiro2018-12-131-1/+0
* virgl: work around bad assumptions in virglrendererErik Faye-Lund2018-12-131-1/+32
* virgl: wrap vertex element state in a structErik Faye-Lund2018-12-132-9/+21
* virgl: simplify virgl_hw_set_index_bufferErik Faye-Lund2018-12-131-3/+2
* virgl: simplify virgl_hw_set_vertex_buffersErik Faye-Lund2018-12-131-4/+2
* docs: update calendar, add news item and link release notes for 18.2.7Juan A. Suarez Romero2018-12-133-7/+8
* docs: add sha256 checksums for 18.2.7Juan A. Suarez Romero2018-12-131-1/+2
* docs: add release notes for 18.2.7Juan A. Suarez Romero2018-12-131-0/+166
* radv: don't check if format is depth in radv_image_can_enable_hile()Samuel Pitoiset2018-12-131-1/+0
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