summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* util/hash_table: replace _mesa_hash_data's fnv1a hash function with xxhashAnthony Pesch2020-01-231-2/+4
| | | | | | | | | | | For most key sizes, xxhash outperforms fnv1a's hash rate substantially (bug 2153). In particular, the V3D driver hashes multiple ~200 byte keys as part of the shader cache lookup which can easily eat up 10-20% of the runtime on the Raspberry Pi. Swapping over to xxhash drops this to ~1% of the runtime. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
* util: move fnv1a hash implementation into its own headerAnthony Pesch2020-01-235-30/+64
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
* util: import xxhashAnthony Pesch2020-01-233-1/+1439
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
* winsys/amdgpu: Close KMS handles for other DRM file descriptionsMichel Dänzer2020-01-232-3/+21
| | | | | | | | | | | | | | | | | | | | | | | When a BO or amdgpu_screen_winsys is destroyed. Should fix leaking such BOs in other DRM file descriptions. v2: * Pass the correct file descriptor to drmIoctl (Pierre-Eric Pelloux-Prayer) * Use _mesa_hash_table_remove v3: * Close handles in amdgpu_winsys_unref as well v4: * Adapt to amdgpu_winsys::sws_list_lock. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2270 Fixes: 11a3679e3aba "winsys/amdgpu: Make KMS handles valid for original DRM file descriptor" Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
* winsys/amdgpu: Re-use amdgpu_screen_winsys when possibleMichel Dänzer2020-01-232-24/+45
| | | | | | | | | | | Namely, if os_same_file_description determined that the DRM file descriptor references the same file description. v2: * Adapt to amdgpu_winsys::sws_list_lock. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
* util: Add os_same_file_description helperMichel Dänzer2020-01-232-0/+31
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
* winsys/amdgpu: Only re-export KMS handles for different DRM FDsMichel Dänzer2020-01-233-11/+32
| | | | | | | | | | | | | When the amdgpu_screen_winsys uses the same FD as the amdgpu_winsys (which is always the case for the first amdgpu_screen_winsys), we can just use bo->u.real.kms_handle. v2: * Also only create the kms_handles hash table if the amdgpu_screen_winsys fd is different from the amdgpu_winsys one. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
* winsys/amdgpu: Keep track of retrieved KMS handles using hash tablesMichel Dänzer2020-01-233-0/+47
| | | | | | | | | | | | | | | | | | | | The assumption being that KMS handles are only retrieved for relatively few BOs, so hash tables should be efficient both in terms of performance and memory consumption. We use the address of struct amdgpu_winsys_bo as the key and its kms_handle field (the KMS handle valid for the DRM file descriptor passed to amdgpu_device_initialize) as the hash value. v2: * Add comment above amdgpu_screen_winsys::kms_handles (Pierre-Eric Pelloux-Prayer) v3: * Protect kms_handles hash table with amdgpu_winsys::sws_list_lock mutex. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
* winsys/amdgpu: Keep a list of amdgpu_screen_winsyses in amdgpu_winsysMichel Dänzer2020-01-232-1/+28
| | | | | | | | v2: * Add dedicated mutex for the list. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
* aco: implement nir_op_f2i64/nir_op_f2u64 on GFX6Samuel Pitoiset2020-01-231-4/+4
| | | | | | | | | V_TRUNC_F64 and V_FLOOR_F64 needs to be lowered on GFX6. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
* aco: implement 64-bit nir_op_ffloor on GFX6Samuel Pitoiset2020-01-231-1/+32
| | | | | | | | | | | | GFX6 doesn't have V_FLOOR_F64, it needs to be lowered. Loosely based on the AMDGPU LLVM backend. Introduce a new function because it will be useful for some other 64-bit operations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
* aco: implement 64-bit nir_op_fround_even on GFX6Samuel Pitoiset2020-01-231-1/+28
| | | | | | | | | GFX6 doesn't have V_RNDNE_F64, it needs to be lowered. Loosely based on the AMDGPU LLVM backend. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
* aco: implement 64-bit nir_op_fceil on GFX6Samuel Pitoiset2020-01-231-1/+18
| | | | | | | | | GFX6 doesn't have V_CEIL_F64, it needs to be lowered. Loosely based on the AMDGPU LLVM backend. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
* aco: implement 64-bit nir_op_ftrunc on GFX6Samuel Pitoiset2020-01-231-1/+45
| | | | | | | | | | | | GFX6 doesn't have V_TRUNC_F64, it needs to be lowered. Loosely based on the AMDGPU LLVM backend. Introduce a new function because it will be useful for some other 64-bit operations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
* aco: implement nir_intrinsic_global_atomic_* on GFX6Samuel Pitoiset2020-01-231-59/+133
| | | | | | | | GFX6 doesn't have FLAT instructions, use MUBUF instructions instead. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
* aco: implement nir_intrinsic_load_global on GFX6Samuel Pitoiset2020-01-231-31/+94
| | | | | | | | GFX6 doesn't have FLAT instructions, use MUBUF instructions instead. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
* aco: implement nir_intrinsic_store_global on GFX6Samuel Pitoiset2020-01-231-43/+98
| | | | | | | | GFX6 doesn't have FLAT instructions, use MUBUF instructions instead. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
* aco: fix wrong IR in nir_intrinsic_load_barycentric_at_sampleSamuel Pitoiset2020-01-231-1/+1
| | | | | | | | | | Only GFX6 was affected, my mistake. The total number of SGPR operands should be 4 when we want to create a vec4. Fixes: dbdf3b3ef97 ("aco: implement nir_intrinsic_load_barycentric_at_sample on GFX6") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
* anv/iris: warn gen12 3DSTATE_HS restrictionLionel Landwerlin2020-01-232-0/+21
| | | | | | | | | | This should never happen but better off documenting it in case someone plays with max threads numbers. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3489> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3489>
* gallium/swr: add option for static linkKrzysztof Raszkowski2020-01-233-80/+159
| | | | | | | | | | Set swr-shared to 'false' to link SWR statically into Mesa. Only one swr arch can be specified if swr-shared is set to false. Reviewed-by: Jan Zielinski <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3510> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3510>
* aco: fix printing assembly with CLRXdisasm on GFX6Samuel Pitoiset2020-01-231-2/+34
| | | | | | | | | | | We thought that CLRXdisasm allowed gfx600 as well as gfx700 but it actually doesn't. Use the family for GFX6 chips instead. Fixes: 0099f85232b ("aco: print assembly with CLRXdisasm for GFX6-GFX7 if found on the system") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3531> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3531>
* clover/meson: Define OpenCL header macrosPierre Moreau2020-01-235-15/+17
| | | | | | | | | | Rather than defining the macros any time right before including an OpenCL header, set Meson to define them for the whole clover project. Reviewed-by: Karol Herbst <[email protected]> Acked-by: Francisco Jerez <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>
* clover: Use the dispatch table type from the OpenCL headersPierre Moreau2020-01-233-930/+4
| | | | | | | | Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2243 Reviewed-by: Karol Herbst <[email protected]> Acked-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>
* include/CL: Update OpenCL headers to latestPierre Moreau2020-01-233-0/+1319
| | | | | | | | | | This latest update contains a new header that defines the dispatch table structure in order to avoid OpenCL implementations having to define it themselves. Reviewed-by: Karol Herbst <[email protected]> Acked-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>
* radv: advertise VK_AMD_shader_fragment_maskSamuel Pitoiset2020-01-233-0/+3
| | | | | | | | | Only for GFX8+ because it's untested on older generations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
* aco: add support for nir_texop_fragment_{mask}_fetchSamuel Pitoiset2020-01-231-4/+13
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
* ac/nir: add support for nir_texop_fragment_{mask}_fetchSamuel Pitoiset2020-01-231-3/+35
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
* nir/lower_input_attachments: lower nir_texop_fragment_{mask}_fetchSamuel Pitoiset2020-01-231-10/+52
| | | | | | | | | These instructions are allowed to fetch from multisampled subpass input attachments. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
* spirv: add support for SpvOpFragment{Mask}FetchAMD operationsSamuel Pitoiset2020-01-231-1/+23
| | | | | | | | | nir_tex_src_ms_index is re-used for the fragment index with nir_texop_fragment_fetch to avoid introducing a new texture source type. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
* nir: add two new texture ops for multisample fragment color/mask fetchesSamuel Pitoiset2020-01-232-0/+9
| | | | | | | | | | | | | | | This introduces: - nir_texop_fragment_mask_fetch (fetch a fragment mask from a compressed multisampled color surface) - nir_texop_fragment_fetch (fetch a color fragment for a particular sample at corresponding fragment mask index). These two texture operations are necessary for implementing SPV_AMD_shader_fragment_mask. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
* spirv: add SpvCapabilityFragmentMaskAMDSamuel Pitoiset2020-01-232-0/+5
| | | | | | | | This new capability is for SPV_AMD_shader_fragment_mask. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
* radv: handle missing implicit subpass dependenciesSamuel Pitoiset2020-01-231-0/+112
| | | | | | | | | | When a subpass doesn't declare an explicit dependency from/to VK_SUBPASS_EXTERNAL, Vulkan says there is an implicit dependency. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330>
* radv: add explicit external subpass dependencies to meta operationsSamuel Pitoiset2020-01-237-14/+296
| | | | | | | | | No functional changes because a subpass dependency with dstStageMask set to VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT is a no-op. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330>
* gallivm: fix find lsbDave Airlie2020-01-231-1/+2
| | | | | | | | | | the GLSL return value is different than the llvm intrinsic. Fixes arb gpu shader5 tests Reviewed-by: Roland Scheidegger <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
* galllivm: fix gather offset castingDave Airlie2020-01-231-2/+4
| | | | | | | cast texture offsets to 32-bit integers Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
* llvmpipe: fix some integer instruction lowering.Dave Airlie2020-01-231-2/+3
| | | | | | | | | We want to lower to shifts for bitfields, and lower ifind_msb. Fixes a bunch of gpu shader5 tests. Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
* gallivm: fix gather component handling.Dave Airlie2020-01-231-2/+3
| | | | | | | Fixes the extended gather test for gpu shader5 Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
* turnip: Add support for uniform texel buffers.Eric Anholt2020-01-234-12/+55
| | | | | | | | | | | | | | | | | | | Pretty straightforward: Port texture descriptor code from freedreno, fill in alignment limits from closed vk, and tu_cmd_buffer.c was already uploading the texture descriptor. This doesn't implement storage texel buffers (required in the compute pipeline) yet, since those will need an IBO descriptor for the store path. Still, making the load path be connected to the texture descriptor won't hurt. Part of #2237 Fixes dEQP-VK.binding_model.shader_access.primary_cmd_buf.uniform_texel_buffer.* Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3522> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3522>
* intel: Fix aux map alignments on 32-bit builds.Kenneth Graunke2020-01-232-5/+5
| | | | | | | | | | | | | | | ALIGN() brilliantly uses uintptr_t, making it unsafe for use with 64-bit GPU addresses in 32-bit builds of the driver. Use align64() instead, which uses uint64_t. Fixes assertion failures when running any 32-bit program on Tigerlake. Fixes: 2e6a7ced4db ("iris/gen12: Write GFX_AUX_TABLE base address register") Fixes: 0d0290bb3f7 ("intel/common: Add surface to aux map translation table support") Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507>
* util: Remove tmp argument from BITSET_FOREACH_SET macroMatt Turner2020-01-239-34/+21
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>
* util: Explain BITSET_FOREACH_SET paramsMatt Turner2020-01-231-0/+8
| | | | | | | | __size, in particular, makes this macro rather confusing to understand how to use. Hopefully this comment saves future users the headache. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>
* lima: implement invalidate_resource()Vasily Khoruzhick2020-01-233-18/+34
| | | | | | | | | | We don't need to resolve invalidated resources, so it should improve performance for applications that are doing this hint. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3476> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3476>
* glsl_to_nir: update interface type properlyTimothy Arceri2020-01-231-2/+4
| | | | | | | | | | | | | Since 76ba225184ed the member variable types were being redefined but we assigned the old interface type to the variable. In a following patch series we will use the types to check if we are dealing with an interface instance when apply GLSL linking rules. Reviewed-by: Alejandro Piñeiro <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
* glsl: count uniform components and storage better in nir linkingTimothy Arceri2020-01-231-4/+13
| | | | | | | | | This helps avoid incorrect validation error when linking glsl shaders and avoids assigning uniform storage slots that will never be used. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
* glsl: fix check for matrices in blocks when using nir uniform linkerTimothy Arceri2020-01-231-4/+3
| | | | | | | | We need to stripe any arrays before checking the type. Here we just use the uniform type which has already be stripped. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
* glsl: remove bogus assert in nir uniform linkingTimothy Arceri2020-01-231-1/+0
| | | | | | | | I'm not sure why this was first added but it causes an assert on any uniform matrix. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
* nir/algebraic: Optimize some 64-bit integer comparisons involving zeroIan Romanick2020-01-231-0/+18
| | | | | | | | | | | | | | | | | | I noticed that we can do better for these kinds of comparisons while working on the lowering for iadd_sat@64 and isub_sat@64. This eliminated 11 instruction from the fs-addSaturate-int64.shader_test. My hope is that this will improve the run-time of int64 tests on Ice Lake. I have no data to support or refute this. Unsurprisingly, no changes on shader-db. v2: Condition the min and max patterns with nir_lower_minmax64. Suggested by Caio. Very long discussion in the MR. :) Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
* anv: Enable SPV_INTEL_shader_integer_functions2 and ↵Ian Romanick2020-01-232-0/+2
| | | | | | | | | | | VK_INTEL_shader_integer_functions2 Currently only implemented in the scalar backend, so only enable for Gen8+. If support for the other opcodes is added to the vec4 backend, Gen7 could be supported. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
* iris: Enable INTEL_shader_integer_functions2Ian Romanick2020-01-232-0/+10
| | | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
* gallium: Add a cap bit for integer multiplication between 32-bit and 16-bitIan Romanick2020-01-233-0/+3
| | | | | | | | | | | | | | Driver supports integer multiplication between a 32-bit integer and a 16-bit integer. If the second operand is 32-bits, the upper 16-bits are ignored, and the low 16-bits are possibly sign extended as necessary. Iris will eventually enable this. Not sure about other drivers. v2: Add default value to u_screen.c. Suggested by Caio. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 08:33:35 +0000