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* configure.ac: report an error if LLVM shared libs are disabled and CL is enabledMarek Olšák2013-10-081-2/+3
| | | | Reviewed-by: Tom Stellard <[email protected]>
* st/mesa: improve format selection for GLESMarek Olšák2013-10-083-1/+40
| | | | Reviewed-by: Wladimir J. van der Laan <[email protected]>
* i915g: Rename sampler to fragment_samplerStéphane Marchesin2013-10-074-9/+9
| | | | Otherwise it is fairly confusing.
* i915g: Fix the sampler bind functionStéphane Marchesin2013-10-071-19/+30
| | | | | | | | The new sampler bind sends us NULL samplers, so we need to count the number of valid samplers ourselves. This fixes ~500 piglit regressions from the sampler rework. While we're at it, let's also support start.
* gen7: Use logical, not physical, dims in 3DSTATE_DEPTH_BUFFER (v2)Chad Versace2013-10-072-4/+4
| | | | | | | | | | | | | | | | | In 3DSTATE_DEPTH_BUFFER, we set Width and Height to the miptree slice's physical dimensions. (Logical and physical dimensions may differ for multisample surfaces). However, in SURFACE_STATE, we always set Width and Height to the slice's logical dimensions. We should do the same for 3DSTATE_DEPTH_BUFFER, because the hw docs say so. No Piglit regressions (-x glx -x glean) on Ivybridge with Wayland. v2: No Piglit regressions, for real this time. Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* doxygen: Generate Doxygen for i965Chad Versace2013-10-073-1/+53
| | | | | | | | | | | Now, one can do the following to generate and read the i965 Doxygen: cd $MESA_TOP/doxygen make firefox i965/index.html Reviewed-by: Frank Henigman <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Remove the "ARF" register file.Matt Turner2013-10-075-16/+6
| | | | | | | | The registers in the architecture register file don't share much in common, so there's no point in grouping them together. Use the HW_REG class instead. The vec4 backend already does this. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fixup for don't dead-code eliminate instructions that write to the ↵Matt Turner2013-10-072-4/+2
| | | | | | | | | | accumulator. Accidentally pushed an old version of the patch. v2: Set destination register using brw_null_reg(). Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Generate code for ir_binop_imul_high.Matt Turner2013-10-073-0/+18
| | | | | | v2: Make accumulator's type match the type of the operation. Noticed by Ken. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the multiplication result's type for the accumulator.Matt Turner2013-10-072-2/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Disable CSE on instructions writing to HW_REG.Matt Turner2013-10-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | CSE would otherwise combine the two mul(8) emitted by [iu]mulExtended: mul(8) acc0 x y mach(8) null x y mov(8) lsb acc0 ... mul(8) acc0 x y mach(8) msb x y Into: mul(8) temp x y mov(8) acc0 temp mach(8) null x y mov(8) lsb acc0 ... mov(8) acc0 temp mach(8) msb x y But mul(8) into the accumulator produces more than 32-bits of precision, which is required and lost if multiplying into a general register and moving to the accumulator. Reviewed-by: Eric Anholt <[email protected]>
* glsl: Implement [iu]mulExtended() built-ins for ARB_gpu_shader5.Matt Turner2013-10-078-1/+49
| | | | | | | | | | These built-ins have two "out" parameters, which makes implementing them efficiently with our current compiler infrastructure difficult. Instead, implement them in terms of the existing ir_binop_mul IR (to return the low 32-bits) and a new ir_binop_mul64 which returns the high 32-bits. v2: Rename mul64 -> imul_high as suggested by Ken. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add Gen assertion checks for newer instructions.Matt Turner2013-10-072-0/+22
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't dead-code eliminate instructions that write to the accumulator.Matt Turner2013-10-072-2/+30
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Generate code for ir_binop_carry and ir_binop_borrow.Matt Turner2013-10-0714-0/+80
| | | | | | Using the ADDC and SUBB instructions on Gen7. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add UD null register helpers.Matt Turner2013-10-072-0/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Implement usubBorrow() built-in for ARB_gpu_shader5.Matt Turner2013-10-071-0/+21
| | | | | | | | | | | | | | i965 implements this with a single (multiple destination) instruction, SUBB. Emitting SUBB directly from usubBorrow() would be ideal, but our optimization passes don't know how to copy with expressions with side-effects. Radeon has an SUBB_UINT instruction that only generates the borrow bit. I've chosen to go this route and implement usubBorrow() by doing the subtraction and the borrow operations separately. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Implement uaddCarry() built-in for ARB_gpu_shader5.Matt Turner2013-10-071-0/+21
| | | | | | | | | | | | | | i965 implements this with a single (multiple destination) instruction, ADDC. Emitting ADDC directly from uaddCarry() would be ideal, but our optimization passes don't know how to copy with expressions with side-effects. Radeon has an ADDC_UINT instruction that only generates the carry bit. I've chosen to go this route and implement uaddCarry() by doing the addition and the carry operations separately. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Add ir_binop_carry and ir_binop_borrow.Matt Turner2013-10-077-0/+42
| | | | | | | | | Calculates the carry out of the addition of two values and the borrow from subtraction respectively. Will be used in uaddCarry() and usubBorrow() built-in implementations. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl_compiler: Enable any extension that any Mesa driver enablesIan Romanick2013-10-071-1/+8
| | | | | | | | | The only GLSL extension that is not enabled is AMD_vertex_shader_layer. I think the standalone-compiler could enable this (as shading language support is complete), but no driver enables it. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_compiler: Sort extensions by nameIan Romanick2013-10-071-8/+11
| | | | | | | Makes it a little easier to see which ones are missing. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_compiler: Always log the compiler diagnosticsIan Romanick2013-10-071-1/+3
| | | | | | | Not just when there's an error. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_compiler: Set max GLSL version on the command lineIan Romanick2013-10-071-12/+173
| | | | | | | | | | Infer whether or not to use ES based on the GLSL version (100 or 300 are for ES). This replaces the --glsl-es command line option. Set various compiler limits based on the minimums required for the specified GLSL version. Signed-off-by: Ian Romanick <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* glsl_compiler: Use no_argument instead of 0 in getopt_long optionsIan Romanick2013-10-071-5/+5
| | | | | | | | The choices aren't just 0 and 1, so using the enum names is much more clear. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_compiler: Re-enable building glsl_compilerIan Romanick2013-10-072-3/+14
| | | | | | | | | | This allows application developers to use Mesa's compiler as a standalone validator for their shaders. This is mostly a revert of commit 569f0e4. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Remove glsl_parser_state MaxVaryingFloats fieldIan Romanick2013-10-073-5/+4
| | | | | | | | | | Pull the data directly from the context like the other varying related limits. The parser state shadow copies were added back when the parser state didn't have a pointer to the context. There's no reason to do it now days. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* glsl: Set gl_MaxVertexOutputs from VertexProgram.MaxOutputComponents etcIan Romanick2013-10-071-2/+2
| | | | | | | | | | | | | | gl_MaxVertexOutputVectors => ctx->Const.VertexProgram.MaxOutputComponents gl_MaxFragmentInputVectors => ctx->Const.FragmentProgram.MaxInputComponents v2: Add types so that the code compiles. Pointed out by Brian. v3: Leave gl_MaxVaryingFloats et al. as-is. Suggested by Paul. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]> [v2] Reviewed-by: Marek Olšák <[email protected]> [v2] Reviewed-by: Paul Berry <[email protected]> [v2]
* glsl: Count shader inputs and outputs separatelyIan Romanick2013-10-073-25/+91
| | | | | | | | | | | | Starting with OpenGL 3.2 input limits and output limits for stages may not match. This means they need to be accounted separately. No piglit regressions. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* glapi: add output info to GetProgramiv's paramsEmilio Pozuelo Monfort2013-10-071-1/+1
| | | | | Signed-off-by: Emilio Pozuelo Monfort <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* clover: fix building with llvm-3.4 since rev191922Laurent Carlier2013-10-071-1/+5
| | | | http://llvm.org/viewvc/llvm-project?view=revision&revision=191922
* st/mesa: silence warning about unhandled ir_query_levels in switchBrian Paul2013-10-071-0/+3
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* radeon/vdpau: only export necessary symbolsChristian König2013-10-073-0/+9
| | | | | | Export only the absolutely necessary symbols in radeon vdpau targets. Signed-off-by: Christian König <[email protected]>
* radeon/uvd: optimize message handling a bitChristian König2013-10-071-44/+53
| | | | | | | No need to keep a copy of the message in system memory anymore, since it should now be in GART memory on newer chips. Signed-off-by: Christian König <[email protected]>
* docs: Mark a few more things as "in progress" in GL3.txt.Kenneth Graunke2013-10-061-2/+2
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* dri/nouveau: add AllocTextureImageBuffer implementationIlia Mirkin2013-10-061-0/+9
| | | | | | | | | This fixes issues where get_rt_format would see a 0 format because the nouveau_surface had not been properly initialized. Fixes crash on supertuxkart startup (which still fails due to out-of-vram issues). Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Francisco Jerez <[email protected]>
* glsl: Fix usage of the wrong union member in ↵Francisco Jerez2013-10-061-2/+2
| | | | | | | | | | | | | | | program_resource_visitor::recursion. In the array-of-struct case, recursion() takes the row_major flag for each iteration from 't->fields.structure[i]', but 't' is not a record type. Inherit the array declaration row_major flag instead. This mistake was found by running piglit on valgrind. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69449 Cc: "9.1 9.2" <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Kenneth Graunke <[email protected]>
* Revert "r600g: only flush the caches that need to be flushed during CP DMA ↵Marek Olšák2013-10-064-139/+28
| | | | | | | | | | | | | | | | | operations" This reverts commit 7948ed1250cae78ae1b22dbce4ab23aceacc6159. It caused graphical corruption. I've got no idea why. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70042 https://bugs.freedesktop.org/show_bug.cgi?id=68451 Conflicts: src/gallium/drivers/r600/evergreen_hw_context.c src/gallium/drivers/r600/r600_hw_context.c src/gallium/drivers/r600/r600_pipe.h
* i965/ivb: Flag RG32F quirk for texture gather regardless of swizzlesChris Forbes2013-10-061-1/+1
| | | | | | | | | | | | As of ARB_gpu_shader5, textureGather doesn't always read the post-swizzle RED channel -- so we can't just look at the red swizzle state. Theoretically we could only flag the quirk if *some* green swizzle is in use, but that's probably more trouble than it's worth. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add support for textureGather(.., comp)Chris Forbes2013-10-061-7/+11
| | | | | | | | | | | - For HSW: Select the channel based on the component selected (swizzle is done in HW) - For IVB: Select the channel based on the swizzle state for the component selected. Only apply the RG32F w/a if we actually want green -- we're about to flag it regardless of swizzle state. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for textureGather(.., comp)Chris Forbes2013-10-061-7/+11
| | | | | | | | | | | - For HSW: Select the channel based on the component selected (swizzle is done in HW) - For IVB: Select the channel based on the swizzle state for the component selected. Only apply the RG32F w/a if we actually want green -- we're about to flag it regardless of swizzle state. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: add ARB_gpu_shader5's additional textureGather signaturesChris Forbes2013-10-061-1/+26
| | | | | | | | | | | - gsampler2DRect support - optional `comp` parameter Future patches will add shadow sampler support and textureGatherOffsets(). Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Add support for specifying the component in textureGatherChris Forbes2013-10-068-7/+42
| | | | | | | | | | | ARB_gpu_shader5 introduces new variants of textureGather* which have an explicit component selector, rather than relying purely on the sampler's swizzle state. This patch adds the GLSL plumbing for the extra parameter. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* docs: mark ARB_conservative_depth done on i965Chris Forbes2013-10-062-1/+2
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965: Enable ARB_conservative_depth for Gen7+.Chris Forbes2013-10-061-0/+1
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/wm: Program correct conservative depth modesChris Forbes2013-10-061-2/+14
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* docs: rephrase 9.2.1, 9.1.7 news itemBrian Paul2013-10-051-9/+3
| | | | Both are bug-fix releases, not new development releases.
* docs: add the MD5 sums for the 9.2.1 and 9.1.7 releasesBrian Paul2013-10-052-2/+6
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* docs: Mark off KHR_debug, update relnotesTimothy Arceri2013-10-052-1/+2
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: add missing break between ir_query_levels and ir_tg4 casesChris Forbes2013-10-051-0/+1
| | | | Signed-off-by: Chris Forbes <[email protected]>
* docs: Mark off ARB_texture_query_levels, update relnotesChris Forbes2013-10-052-1/+3
| | | | Signed-off-by: Chris Forbes <[email protected]>
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