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* radeonsi: fix is_oneway_access_only for image storesMarek Olšák2018-11-281-12/+37
| | | | We need to look at the Dst for image stores.
* radeonsi: use structured buffer intrinsics for image viewsMarek Olšák2018-11-282-10/+42
| | | | to stop using the workaround in si_make_buffer_descriptor.
* radeonsi: clean up primitive binning enablementMarek Olšák2018-11-281-11/+16
| | | | | | no change in behavior. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* virgl: fix undefined shift to use unsigned.Dave Airlie2018-11-291-1/+1
| | | | | | Ported from virglrenderer. Signed-off-by: Dave Airlie <[email protected]>
* r600: make suballocator 256-bytes alignDave Airlie2018-11-291-1/+1
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108311 Cc: <[email protected]>
* intel/compiler: Use nir's info when checking uses_streams.Kenneth Graunke2018-11-281-1/+1
| | | | | | | | | Vulkan and Gallium don't use Mesa's gl_program data structure, so they can't poke at 'prog'. But we can simply use the copy of the shader info stored with the NIR shader, which is guaranteed to exist. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir/derefs: Add a nir_derefs_do_not_alias enum valueJason Ekstrand2018-11-282-3/+4
| | | | | | This makes some of the code more clear. Reviewed-by: Thomas Helland <[email protected]>
* egl: add missing #include <stddef.h> in egldevice.hGurchetan Singh2018-11-281-1/+1
| | | | | | | | | | | | | | | | | | Otherwise, I get this error: main/egldevice.h:54:13: error: ‘NULL’ undeclared (first use in this function) dev = NULL; ^~~~ with this config: ./autogen.sh --enable-gles1 --enable-gles2 --with-platforms='surfaceless' --disable-glx --with-dri-drivers="i965" --with-gallium-drivers="" --enable-gbm v3: Use stddef.h (Matt) v4: Modify commit message (Eric) Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* gallivm: Use nextafterf(0.5, 0.0) as rounding constantMatt Turner2018-11-281-1/+1
| | | | | | | | | | | The common truncf(x + 0.5) fails for the floating-point value just less than 0.5 (nextafterf(0.5, 0.0)). nextafterf(0.5, 0.0) + 0.5, after rounding is 1.0, thus truncf does not produce the desired value. The solution is to add nextafterf(0.5, 0.0) instead of 0.5 before truncating. This works for all values. Reviewed-by: Roland Scheidegger <[email protected]>
* docs: update calendar, add news item and link release notes for 18.2.6Juan A. Suarez Romero2018-11-283-7/+8
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* docs: add sha256 checksums for 18.2.6Juan A. Suarez Romero2018-11-281-1/+2
| | | | | Signed-off-by: Juan A. Suarez Romero <[email protected]> (cherry picked from commit cfd1f8b92cae9dde3e5bed42109b5142f50a2ee5)
* docs: add release notes for 18.2.6Juan A. Suarez Romero2018-11-281-0/+178
| | | | | Signed-off-by: Juan A. Suarez Romero <[email protected]> (cherry picked from commit 3e741344d79e3ae67b1ad645e7d56fe6c0fb2ae2)
* egl/wayland: rather obvious build fixNicolai Hähnle2018-11-281-2/+2
| | | | | Fixes: ce74a7bb8de7 ("egl/wayland: plug memory leak in drm_handle_device()") Fixes: c59d3aa4b9bc ("egl/wayland: bail out when drmGetMagic fails")
* winsys/amdgpu: explicitly declare whether buffer_map is permanent or notNicolai Hähnle2018-11-2817-62/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new driver-private transfer flag RADEON_TRANSFER_TEMPORARY that specifies whether the caller will use buffer_unmap or not. The default behavior is set to permanent maps, because that's what drivers do for Gallium buffer maps. This should eliminate the need for hacks in libdrm. Assertions are added to catch when the buffer_unmap calls don't match the (temporary) buffer_map calls. I did my best to update r600 for consistency (r300 needs no changes because it never calls buffer_unmap), even though the radeon winsys ignores the new flag. As an added bonus, this should actually improve the performance of the normal fast path, because we no longer call into libdrm at all after the first map, and there's one less atomic in the winsys itself (there are now no atomics left in the UNSYNCHRONIZED fast path). Cc: Leo Liu <[email protected]> v2: - remove comment about visible VRAM (Marek) - don't rely on amdgpu_bo_cpu_map doing an atomic write Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add amdgpu_winsys_bo::lockNicolai Hähnle2018-11-283-13/+20
| | | | | | | We'll use it in the upcoming mapping change. Sparse buffers have always had one. Reviewed-by: Marek Olšák <[email protected]>
* vulkan/wsi: fix s/,/;/ typoEric Engestrom2018-11-281-2/+2
| | | | | | Fixes: 59e58c348e6af16a5f2dd "vulkan/wsi: Only wait on semaphores on the first swapchain" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* egl/wayland: plug memory leak in drm_handle_device()Emil Velikov2018-11-281-0/+2
| | | | | | | | | | As we fail to open the node, we leak the node/device name. v2: Log and then free() (Eric) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* egl/wayland: bail out when drmGetMagic failsEmil Velikov2018-11-281-1/+8
| | | | | | | | | | | | | Currently as the function fails, we pass uninitialized data to the authentication function. Stop doing that and print an warning when the function fails. v2: Plug memory leak in error path (Eric) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> (v1) Reviewed-by: Eric Engestrom <[email protected]>
* wsi/display: fix mem leak when freeing swapchainsEric Engestrom2018-11-281-0/+2
| | | | | | Fixes: da997ebec92942193955 "vulkan: Add KHR_display extension using DRM [v10]" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Keith Packard <[email protected]>
* i965: Set the FBO error state INCOMPLETE_ATTACHMENT only for SRGB_R8Gert Wollny2018-11-281-3/+10
| | | | | | | | | | | | | | | Originally the driver reported GL_FRAMEBUFFER_UNSUPPORTED in all cases, adding more specific error messages was not correct and broke many tests. Mostly revert this and only report GL_FRAMEBUFFER_INCOMPLETE_ATTACHMENT for MESA_FORMAT_R_SRGB8. Fixes: ebcde3454552adc6d3fea8af2207aafaba857796 i965: be more specific about FBO completeness errors Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108805 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Explicitely handle swizzles for MESA_FORMAT_R_SRGB8Gert Wollny2018-11-281-3/+7
| | | | | | | | | | | | The format is emulated by using ISL_FORMAT_L8_SRGB, therefore we need to force swizzles for the GBA channels. However, doing this only based on the data type GL_RED breaks other formats, therefore, test specifically for the format. Fixes: c5363869d4971780401b21bb75083ef2518c12be i965: Force zero swizzles for unused components in GL_RED and GL_RG Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* virgl: Don't try handling server fences when they are not supportedGert Wollny2018-11-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | vtest doesn't implement the according API and would segfault: Program received signal SIGSEGV, Segmentation fault. #0 0x0000000000000000 in ?? () #1 in virgl_fence_server_sync at src/gallium/drivers/virgl/virgl_context.c:1049 #2 in st_server_wait_sync at src/mesa/state_tracker/st_cb_syncobj.c:155 so just don't do the call when the function pointers are not set. Fixes dEQP: dEQP-GLES3.functional.fence_sync.wait_sync_smalldraw dEQP-GLES3.functional.fence_sync.wait_sync_largedraw Fixes: d1a1c21e7621b5177febf191fcd3d3b8ef69dc96 virgl: native fence fd support Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Robert Foss <[email protected]>
* virgl,vtest: Initialize return valueGert Wollny2018-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Avoids: Conditional jump or move depends on uninitialised value(s) at 0x9E2B39F: virgl_vtest_winsys_resource_cache_create (virgl_vtest_winsys.c:379) by 0x9E2725F: virgl_buffer_create (virgl_buffer.c:169) by 0x9E246D5: virgl_resource_create (virgl_resource.c:60) by 0xA0C1B9F: bufferobj_data (st_cb_bufferobjects.c:344) by 0xA0C1B9F: st_bufferobj_data (st_cb_bufferobjects.c:390) by 0x9F4ACE3: vbo_use_buffer_objects (vbo_exec_api.c:1136) by 0xA0C68C3: st_create_context_priv (st_context.c:416) by 0xA0C707A: st_create_context (st_context.c:598) by 0x9F81C6B: st_api_create_context (st_manager.c:918) by 0x9BBE591: dri_create_context (dri_context.c:161) by 0x9BB6931: driCreateContextAttribs (dri_util.c:473) by 0x4E97A44: drisw_create_context_attribs (drisw_glx.c:630) by 0x4E7C591: glXCreateContextAttribsARB (create_context.c:78) Uninitialised value was created by a stack allocation at 0x9E2B249: virgl_vtest_winsys_resource_cache_create (virgl_vtest_winsys.c:342) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Robert Foss <[email protected]>
* intel/compiler: fix register allocation in opt_peephole_selIago Toral Quiroga2018-11-281-2/+1
| | | | | | This wasn't handling 64-bit cases properly. Found by inspection. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Remove unused member variableMatt Turner2018-11-271-4/+0
| | | | Reviewed-by: Tapani Pälli <[email protected]>
* nir: Call fflush() at the end of nir_print_shader()Matt Turner2018-11-271-0/+1
| | | | | | | | We normally call with stderr which is unbuffered, so this won't affect that, but it does let me call nir_print_shader(nir, fopen("log", "w+")) from gdb and actually get the whole shader in my file. Reviewed-by: Tapani Pälli <[email protected]>
* v3d: Add renderonly support.Eric Anholt2018-11-276-5/+77
| | | | | | I've been using this with the kmsro series to test v3d on VKMS without my old KMS hack in the v3d kernel driver. KMSRO still needs some cleanup, but v3d RO support seems reasonable.
* gallium: Remove unused variable in u_tests.Eric Anholt2018-11-271-1/+0
| | | | | Fixes: 0d17b685b1ff ("gallium/u_tests: add a compute shader test that clears an image") Reviewed-by: Marek Olšák <[email protected]>
* radv: Align large buffers to the fragment size.Bas Nieuwenhuizen2018-11-271-1/+5
| | | | | | | | | | | | | | | | Improves performance in Talos by about 15% (and significant improvements in RotR and possibly other but did not bench with final patch) on kernel 4.19 and earlier. On 4.20+ a similar effect comes from 433ca054949a "drm/amdgpu: try allocating VRAM as power of two" v2: Do not impact the alignment of the physical memory. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> CC: <[email protected]>
* freedreno: implements get_sample_positionHyunjun Ko2018-11-271-0/+45
| | | | | | | | | | Since 1285f71d3e landed, it needs to provide apps with proper sample position for MSAA. Currently no way to query this to hw, these are taken from blob driver. Fixes: dEQP-GLES31.functional.texture.multisample.samples_#.sample_position Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: also set FSSUPERTHREADENABLERob Clark2018-11-271-0/+1
| | | | | | | | | | We set equiv bit in SP_FS_CTRL_REG0. Somehow the hw doesn't hang with this mismatched config, but does run slower. It is faster with either neither bit set, or both bits set, but both is the fastest of the three configurations. Worth a bit over 10% gain in glmark2. Spotted-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: use MSM_BO_SCANOUT with scanout buffersJonathan Marek2018-11-273-1/+7
| | | | Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: use GENERIC instead of TEXCOORD for blit programJonathan Marek2018-11-271-1/+1
| | | | | | | blip_fp uses GENERIC as input, so blit_vp should match for linking Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: a2xx texture updateJonathan Marek2018-11-279-20/+212
| | | | | | | | | | | Adds all missing texture related logic. For everything to work it also needs changes to ir2/fd2_program, which are part of the ir2 update patch. Note: it needs rnndb update Signed-off-by: Jonathan Marek <[email protected]> [remove stray patch] Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: Compute depth base in gmem correctlyJonathan Marek2018-11-271-5/+7
| | | | | | | | Note: it needs rnndb update Signed-off-by: Marek Vasut <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: set VIZ_QUERY_ID on a20xJonathan Marek2018-11-271-0/+5
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: add missing a20x idsJonathan Marek2018-11-271-0/+2
| | | | | | | | 200: 256KiB GMEM A200 (imx53) 201: 128KiB GMEM A200 (imx51) Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: fix POINT_MINMAX_MAX overflowJonathan Marek2018-11-271-1/+1
| | | | | | | As it stands, it overflows to zero. Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: a2xx: fd2_draw updateJonathan Marek2018-11-276-20/+114
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* nir: add fceil loweringJonathan Marek2018-11-272-0/+4
| | | | | | | | | lowers ceil(x) as -floor(-x) Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-11-277-39/+287
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: set guardband clipRob Clark2018-11-274-7/+57
| | | | | | | | | On older gens, the CLIP_ADJ bitfields were actually 3.6 fixed point. Which might make more sense. Although this formula comes up with values pretty close to what blob does for various viewport sizes (for at least a5xx and a6xx), and seems to work. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: disable LRZ for z32Rob Clark2018-11-271-1/+13
| | | | | | | | | f6131d4ec7a had the side effect of enabling LRZ w/ 32b depth buffers. But there are some bugs with this, which aren't fully understood yet, so for now just skip LRZ w/ z32.. Fixes: f6131d4ec7a freedreno/a6xx: Clear z32 and separate stencil with blitter Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: Clear gmem buffers at flush timeKristian H. Kristensen2018-11-274-178/+180
| | | | | | | | | We generate an IB to clear the gmem at flush time and jump to it before rendering each tile. This lets us get rid of the command stream patching for gmem offsets. Signed-off-by: Kristian H. Kristensen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: Move resolve blits to an IBKristian H. Kristensen2018-11-273-8/+29
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: Move restore blits to IBKristian H. Kristensen2018-11-273-19/+49
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* mesa/st: better colormask check for clear fallbackRob Clark2018-11-271-2/+8
| | | | | | | | | For RGB surfaces (for example) we don't really care that the colormask is 0x7 instead of 0xf. This should not trigger clear_with_quad() slowpath. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/st: swap order of clear() and clear_with_quad()Rob Clark2018-11-271-3/+3
| | | | | | | | | | | If we can't clear all the buffers with pctx->clear() (say, for example, because of ColorMask), push the buffers we *can* clear with pctx->clear() first. Tilers want to see clears coming before draws to enable fast- paths, and clearing one of the attachments with a quad-draw first confuses that logic. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno: move ir3 to common locationRob Clark2018-11-2744-110/+145
| | | | | | | | | | | | | | | | Move (most of) the ir3 compiler to src/freedreno/ir3 so that it can be re-used by some future vulkan driver. The parts that are gallium specific have been refactored out and remain in the gallium driver. Getting the move done now so that it can happen before further refactoring to support a6xx specific instructions. NOTE also removes ir3_cmdline compiler tool from autotools build since that was easier than fixing it and I normally use meson build. Waiting patiently for the day that we can remove *everything* from the autotools build. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove u_inlines usageRob Clark2018-11-271-10/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
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