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* gallium: move ddebug, noop, rbug, trace to auxiliary to improve build timesMarek Olšák2018-04-1379-386/+96
| | | | which also simplifies the build scripts.
* radeonsi: make sure CP DMA is idle at the end of IBsMarek Olšák2018-04-133-2/+16
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* gallium/hud: add a simple HUD view that only draws textMarek Olšák2018-04-132-15/+60
| | | | | | | | | | | Add this prefix to the env var: "simple," For example: GALLIUM_HUD=simple,fps The X coordinates are the same, but the Y coordinates are different, because there is only text. '+' happens to behave the same as "\n". ',' happens to behave the same as "\n\n".
* mesa: Include unistd.h in program_lexerDylan Baker2018-04-131-0/+1
| | | | | | | | | | | | Which was previously provided implicitly by mtypes.h CC: Marek Olšák <[email protected]> CC: Mark Janes <[email protected]> Fixes: 43d66c8c2d4d3d4dee1309856b6ce6c5393682e5 ("mesa: include mtypes.h less") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radeonsi: always prefetch later shaders after the draw packetMarek Olšák2018-04-133-26/+75
| | | | | | | | | so that the draw is started as soon as possible. v2: only prefetch the API VS and VBO descriptors Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: emit shader pointers before cache flushes & waitsMarek Olšák2018-04-131-13/+7
| | | | | | | | This code was written with the constant engine in mind. We can simplify it now. Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: don't use the workaround for gather4 + stencilMarek Olšák2018-04-131-2/+11
| | | | | | | it doesn't seem to be needed. Acked-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: disable TC-compat HTILE on Tonga and IcelandMarek Olšák2018-04-131-0/+7
| | | | | Acked-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: force 2D tiling on VI only when TC-compat HTILE is really enabledMarek Olšák2018-04-131-9/+7
| | | | | | | just pass the flag that indicates it. Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: don't flush HTILE if there is no HTILE clearMarek Olšák2018-04-131-2/+2
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: merge 2 identical if statements in si_clearMarek Olšák2018-04-131-9/+2
| | | | | | | and other cleanups Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: don't do GFX-specific texture decompression for computeMarek Olšák2018-04-131-10/+10
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: simplify generating the renderer stringMarek Olšák2018-04-131-11/+8
| | | | | | | HAVE_LLVM > 0 is a tautology. Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* winsys/amdgpu: allow local BOs on APUsMarek Olšák2018-04-131-1/+2
| | | | | | | Local BOs ignore BO priorities, and we don't need those on APUs. Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* getteximage: assume texture image is empty for non defined levelsJuan A. Suarez Romero2018-04-131-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code is returning an INVALID_OPERATION when trying to use getTextureImage() on a level that has not been explicitly defined. That is, we define a mipmapped Texture2D with 3 levels, and try to use GetTextureImage() for the 4th levels, and INVALID_OPERATION is returned. Nevertheless, such case is not listed as an error in OpenGL 4.6 spec, section 8.11.4 ("Texture Image Queries"), where all the case errors for this function are defined. So it seems this is a valid operation. On the other hand, in section 8.22 ("Texture State and Proxy State") it states: "Each initial texture image is null. It has zero width, height, and depth, internal format RGBA, or R8 for buffer textures, component sizes set to zero and component types set to NONE, the compressed flag set to FALSE, a zero compressed size, and the bound buffer object name is zero." We can assume that we are reading this initialized empty image when calling GetTextureImage() with a non defined level. With this assumption, we will reach one of the other error cases defined for the functions. In the end this means that we would end up returning INVALID_VALUE to the caller. This fixes arb_get_texture_sub_image piglit tests. v2: just return INVALID_VALUE if there is no defined level (Iago) Signed-off-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* gettextureimage: verify cube map is completeJuan A. Suarez Romero2018-04-131-9/+14
| | | | | | | | | | | | | | | According to OpenGL 4.6 spec, section 8.11.4 ("Texture Image Queries"), relative to errors for GetTexImage, GetTextureImage, and GetnTexImage: "An INVALID_OPERATION error is generated by GetTextureImage if the effective target is TEXTURE_CUBE_MAP or TEXTURE_CUBE_MAP_ARRAY, and the texture object is not cube complete or cube array complete, respectively." This fixes arb_get_texture_sub_image piglit tests. Signed-off-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* gettextsubimage: verify zoffset and depth are correctJuan A. Suarez Romero2018-04-131-2/+2
| | | | | | | | | | | | | | | | | | | According to OpenGL 4.6 spec, section 8.11.4 ("Texture Image Queries"), relative to errors for GetTextureSubImage() function: "An INVALID_VALUE error is generated if the effective target is TEXTURE_1D and either yoffset is not zero, or height is not one. An INVALID_VALUE error is generated if the effective target is TEXTURE_1D, TEXTURE_1D_ARRAY, TEXTURE_2D or TEXTURE_RECTANGLE, and either zoffset is not zero, or depth is not one." The commit fixes the check for height and depth. This fixes arb_get_texture_sub_image piglit tests. Signed-off-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: free debug messages when destroying the debug stateTimothy Arceri2018-04-131-22/+23
| | | | | | | Fixes: 04a8baad3721 "mesa: refactor _mesa_PopDebugGroup and _mesa_free_errors_data" Reviewed-by: Iago Toral Quiroga <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98281
* mesa: fix x86 buildsTimothy Arceri2018-04-131-0/+1
| | | | Fixes: 43d66c8c2d4d "mesa: include mtypes.h less"
* Fix make checkMarek Olšák2018-04-121-0/+1
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* Fix scons buildMarek Olšák2018-04-127-1/+13
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* mesa: include mtypes.h lessMarek Olšák2018-04-12177-367/+477
| | | | | | | | | | - remove mtypes.h from most header files - add main/menums.h for often used definitions - remove main/core.h v2: fix radv build Reviewed-by: Brian Paul <[email protected]>
* mesa: include dispatch.h lessMarek Olšák2018-04-1220-20/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* radv: Implement VK_EXT_vertex_attribute_divisor.Bas Nieuwenhuizen2018-04-126-11/+50
| | | | | | | Pretty straight forward, just pass the divisors through the shader key and then do a LLVM divide. Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/surface: Allow S swizzle for displayable surfaces.Bas Nieuwenhuizen2018-04-121-2/+5
| | | | | | | | | | | For dcn1 && < 64 bpp displayable surfaces, addrlib only accepts S swizzles. At the same time addrlib prefers D swizzles is allowed, so we can just allow S swizzles as fallback. Fixes: b64b712558 "ac/surface/gfx9: request desired micro tile mode explicitly" Reviewed-by: Marek Olšák <[email protected]>
* broadcom/vc5: Fix a stray '`' in a comment.Eric Anholt2018-04-121-1/+1
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* broadcom/vc5: Update the UABI for in/out syncobjsEric Anholt2018-04-129-90/+55
| | | | | | | | | This is the ABI I'm hoping to stabilize for merging the driver. seqnos are eliminated, which allows for the GPU scheduler to task-switch between DRM fds even after submission to the kernel. In/out sync objects are introduced, to allow the Android fencing extension (not yet implemented, but should be trivial), and to also allow the driver to tell the kernel to not start a bin until a previous render is complete.
* broadcom/vc5: Drop the finished_seqno optimization.Eric Anholt2018-04-122-11/+0
| | | | | With the DRM scheduler changes, I'm about to remove all seqnos from the UABI.
* broadcom/vc5: Drop the throttling code.Eric Anholt2018-04-121-9/+0
| | | | | Since I'll be using the DRM scheduler, we won't run into the problem of a runaway client starving other clients of GPU time.
* broadcom/vc5: Move flush_last_load into load_general, like for stores.Eric Anholt2018-04-121-28/+29
| | | | | | | This should avoid mistakes with not flushing as we change the series of loads. Already, it fixes a hopefully unreachable case where we were emitting just the TILE_COORDINATES and not the dummy store that needs to go with it.
* broadcom/vc5: Rename read_but_not_cleared to loads_pending.Eric Anholt2018-04-121-13/+13
| | | | | This is a more obvious name for what the variable means, and matches what it's called for stores.
* broadcom/vc5: Refactor the implicit coords/stores_pending logic.Eric Anholt2018-04-121-23/+13
| | | | | Since I just fixed a bug due to forgetting to do these right, do it once in the helper func.
* broadcom/vc5: Emit missing TILE_COORDINATES_IMPLICIT in separate z/s stores.Eric Anholt2018-04-121-5/+16
| | | | | Fixes a simulator assertion failure in KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8
* broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.Eric Anholt2018-04-121-0/+8
| | | | | | | This was dying in the simulator on GTF-GLES3.gtf.GL3Tests.packed_depth_stencil.packed_depth_stencil_blit. We'll need to do basically the same thing as Z32F/S8 does in the MSAA Z24S8 case.
* broadcom/vc5: Fix MSAA depth/stencil size setup.Eric Anholt2018-04-121-2/+4
| | | | | | | The v3dX(get_internal_type_bpp_for_output_format)() call only handles color output formats (which overlap in enum numbers with depth output formats), so for depth we just need to take the normal cpp times the number of samples.
* st/va: add VP9 config to enable profile2Leo Liu2018-04-122-1/+5
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: use PIPE_FORMAT_P016 format for VP9 profile2Leo Liu2018-04-121-1/+2
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add VP9 profile2 supportLeo Liu2018-04-121-0/+16
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* vl: add VP9 profile2 supportLeo Liu2018-04-122-1/+3
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add VP9 config to enable profile0Leo Liu2018-04-122-1/+5
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: parse VP9 uncompressed frame headerLeo Liu2018-04-123-1/+239
| | | | | | | To get some of UVD required parameters. Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add slice parameter handling for VP9Leo Liu2018-04-121-1/+24
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add picture parameter handling for VP9Leo Liu2018-04-121-1/+51
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add handles for VP9 buffersLeo Liu2018-04-125-2/+54
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add VP9 picture to contextLeo Liu2018-04-122-0/+5
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: cap VP9 support to progressive bufferLeo Liu2018-04-121-0/+2
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: cap VP9 support to RavenLeo Liu2018-04-121-0/+4
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add VP9 context bufferLeo Liu2018-04-121-0/+26
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: get VP9 msg bufferLeo Liu2018-04-122-1/+176
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: fill probability table to prob buffersLeo Liu2018-04-121-0/+38
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
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