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* i965: Reduce passing 2x32b of reloc_domains to 2 bitsChris Wilson2017-08-0424-293/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel only cares about whether the object is to be written to or not, only reduces (reloc.read_domains, reloc.write_domain) down to just !!reloc.write_domain. When we use NO_RELOC, the kernel doesn't even read those relocs and instead userspace has to pass that information in the execobject.flags. We can simplify our reloc api by also removing the unused read/write domains and only pass the resultant flags. The caveat to the above are when we need to make the kernel aware that certain objects need to take into account different work arounds. Previously, this was done using the magic (INSTRUCTION, INSTRUCTION) reloc domains. NO_RELOC requires this to be passed in the execobject flags as well, and now we push that up the callstack. The API is more compact, more expressive of what happens underneath, but unfortunately requires more knowledge of the system at the point of use. Conversely it also means that knowledge is specific and not generally applied and so not overused. text data bss dec hex filename 8502991 356912 424944 9284847 8dacef lib/i965_dri.so (before) 8500455 356912 424944 9282311 8da307 lib/i965_dri.so (after) v2: (by Ken) Rebase. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert reloc.target_handle into an index for I915_EXEC_HANDLE_LUTKenneth Graunke2017-08-041-2/+2
| | | | | | | | | | | | | | | | | | | Based on a patch by Chris Wilson (who also wrote this commit message). Passing the index of the target buffer via the reloc.target_handle is marginally more efficient for the kernel (it can avoid some allocations, and can use a direct lookup rather than a hash or search). It is also useful for ourselves as we can use the index into our exec_bos for other tasks. v2: Only enable HANDLE_LUT if we can use BATCH_FIRST and thereby avoid a post-processing loop to fixup the relocations. v3: Move kernel probing from context creation to screen init. Use batch->use_exec_lut as it more descriptive of what's going on (Daniel) v4: Kernel features already exists, use it for BATCH_FIRST Rename locals to preserve current flavouring v5: Squash in "always insert batch bo first" v6: (by Ken) Split out BATCH_FIRST from HANDLE_LUT.
* i965: Use a C99 initializer for new validation list entries.Kenneth Graunke2017-08-041-10/+7
| | | | | | More succinct - we can skip a bunch of = 0 lines. Extracted from a patch by Chris Wilson.
* i965: Simplify some bo != batch->bo special cases.Kenneth Graunke2017-08-041-27/+19
| | | | | | | | Extracted from a patch by Chris Wilson. Now that the batch is always at the front of the validation list, we don't need to special case it - the usual "go find an existing BO" code will work just fine.
* i965: Use I915_EXEC_BATCH_FIRST when available.Kenneth Graunke2017-08-044-10/+33
| | | | | | This will make it easier to use I915_EXEC_HANDLE_LUT. Based on a patch by Chris Wilson.
* i965: Move add_exec_bo()Chris Wilson2017-08-041-53/+53
| | | | | | | | | | To avoid a forward declaration in the next patch, move the definition of add_exec_bo() earlier. v2: (by Ken) redo move. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Ignore reloc read/write domainsChris Wilson2017-08-041-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | Since before the kernel supported I915_EXEC_NO_RELOC, long before our minimum kernel requirement, the kernel unconditionally invalidated all GPU TLBs before a batch and flushed all GPU caches after a batch. At that moment, the only use for read/write domain was for activity tracking, ensuring that future reads waited for the last writer and future writes waited for all reads. This only requires a single bit in the execbuf interface which can be supplied via the NO_RELOC interface, making the use of relocation domains entirely redundant. Trimming the excess writes into the array allows the compiler to be much more frugal: text data bss dec hex filename 8493790 357184 424944 9275918 8d8a0e i965_dri.baseline 8493758 357184 424944 9275886 8d89ee i965_dri.so (This text improvement really does come from dropping domains, not from the new use of C99 initializers.) Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use I915_EXEC_NO_RELOCChris Wilson2017-08-041-7/+33
| | | | | | | | | | | | If we correctly fill the batch with the right relocation value, and that matches the expected location of the object, we can then tell the kernel it can forgo checking each individual relocation by only checking whether the object moved. v2: Rebase to apply ahead of I915_EXEC_HANDLE_LUT Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Initialize flags to 0 and |= in new flags.Kenneth Graunke2017-08-041-3/+3
| | | | This makes it a bit easier to add new unconditional flags.
* i965: Make add_exec_bo return the validation list index.Kenneth Graunke2017-08-041-4/+5
| | | | This will be useful for I915_EXEC_HANDLE_LUT and I915_EXEC_NO_RELOC.
* i965: Track last location of bo used for the batchChris Wilson2017-08-043-2/+27
| | | | | | | | | | | | | | Borrow a trick from anv, and use the last known index for the bo to skip a search of the batch->exec_bo when adding a new relocation. In defence against the bo being used in multiple batches simultaneously, we check that this slot exists and points back to us. v2: Also update brw_batch_references() v3: Reset bo->index on creation (Daniel) v4: Improved explanation of bo->index (Kenneth) Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Always use the pre-computed offset for the relocation entryChris Wilson2017-08-042-42/+36
| | | | | | | | | | | | | | | | We must be careful to only compute the address once based on the per-context information (rather than accessing the unlocked global bo->offset64) so that the value in the batch does match the reloc.presumed_offset we declare to the kernel. Otherwise, highly unlikely, but we may see GPU hangs in multithreaded users. The only real complication here is isl_surf_fill_state() which needs to adjust the reloc.delta to both general a tile offset and to encode state into the lower 12 bits. (Rebased on ISL changes by Ken.) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make brw_emit_reloc assert that the target BO is non-NULL.Kenneth Graunke2017-08-041-0/+2
| | | | | | You need an actual BO to emit a relocation to it. Suggested by me, authored by Chris, split out of a larger patch.
* configure.ac: drop manual detection of expat header/libraryEmil Velikov2017-08-041-7/+1
| | | | | | | | | | | | Use the .pc file, as provided by version prior 2.1.0 onward and dropping the manual header/library check. Version 2.1.0 was released back in Mar 2012 and all major distributions use it. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (IRC)
* configure.ac: unconditionally check for expatEmil Velikov2017-08-041-9/+9
| | | | | | | | | | | | | | Earlier commits moved the xmlconfig library to a wider userbase. Thus having the check within --enable-dri is insufficient. Upon closer look, nine needed it from it's early days - 948e6c52282 ("nine: Add drirc options (v2)") Fixes: 601093f95ddf ("xmlconfig: move into src/util") Cc: Axel Davy <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (IRC)
* android: radeonsi: add nir include pathsMauro Rossi2017-08-041-1/+2
| | | | | | | | | | | | | | Android build changes to avoid the following building error: target C: libmesa_pipe_radeonsi <= external/mesa/src/gallium/drivers/radeonsi/si_pipe.c ... In file included from external/mesa/src/gallium/drivers/radeonsi/si_pipe.c:38: external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found ^ 1 error generated. Fixes: da62a31c5b "radeonsi: add nir include paths" Reviewed-by: Emil Velikov <[email protected]>
* i965: Prefer using streaming reads from WC mmapsChris Wilson2017-08-041-3/+15
| | | | | | | | | | For buffer objects, where we primarily expect to be writing to them and so already have a WC mmap (for !llc access) reusing the existing mmap and keeping the buffer out of the CPU cache seems preferable. Cc: Kenneth Graunke <[email protected]> Cc: Matt Turner <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* pipe-loader: fix swrast probingNicolai Hähnle2017-08-041-1/+1
| | | | | | | | Missed updating this caller of pipe_loader_find_module. Fixes: 0d7d60b7ea ("pipe-loader: pass only the driver_name to pipe_loader_find_module") Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* pipe-loader: remove config from pipe_loader_create_screenNicolai Hähnle2017-08-0413-26/+19
| | | | | | | | | | | | The config passed into the screen should be independent from the state tracker, because at least in the case of radeonsi, the screen structure can be shared between different state trackers. Incidentally, this also fixes crashes that were recently introduced. Fixes: a35a9e7c ("gallium: add driconf options to pipe_screen_config") Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: get rid of pipe_screen_config::flagsNicolai Hähnle2017-08-046-23/+7
| | | | | | | | | | | They were set only by the DRI state tracker, which is problematic when radeonsi is used with different state trackers in the same process. Also, we don't need them anymore. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: set drirc compiler options before calling common screen initNicolai Hähnle2017-08-044-13/+14
| | | | | | | | Also, access the options directly, allowing us to get rid of the PIPE_SCREEN_xxx flags. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* util: Makefile.am: add merge_driinfo.py in extra distJuan A. Suarez Romero2017-08-041-0/+1
| | | | Reviewed-by: Emil Velikov <[email protected]>
* radeonsi: Makefile.sources: include driinfo_radeonsi.hJuan A. Suarez Romero2017-08-041-0/+1
| | | | Reviewed-by: Emil Velikov <[email protected]>
* anv: Makefile.vulkan.am: ICD json files are now generated with pythonJuan A. Suarez Romero2017-08-041-2/+1
| | | | | | | | | Commit 0ab04ba979b7 (anv: Use python to generate ICD json files) changed the way ICD json files are created. Remove the old .in files from extra dist, and add the python script. Reviewed-by: Emil Velikov <[email protected]>
* radv: also fix texture image descriptors for mipmap tile swizzleDave Airlie2017-08-041-1/+2
| | | | | | | This fixes the image descriptors for mipmapped tile swizzle Fixes: 2b7e8556 (ac/surface: enable tile swizzle for mipmapped textures) Signed-off-by: Dave Airlie <[email protected]>
* radv: fix tile swizzle regression on mipmaps.Dave Airlie2017-08-041-5/+6
| | | | | | | | | | | When Marek enabled mipmapped swizzle, radv didn't have the code in place to handle it. This fixes the regression. I'll look more into GFX9 once I have a vega card (soon). Fixes: 2b7e8556 (ac/surface: enable tile swizzle for mipmapped textures) Signed-off-by: Dave Airlie <[email protected]>
* pipe-loader: Add driver build directory for si_driinfo.h include pathMichel Dänzer2017-08-041-0/+1
| | | | | | | | | | | | | | | | | Fixes out-of-tree build failure: .../src/gallium/targets/pipe-loader/pipe_radeonsi.c: In function ‘drm_configuration’: .../src/gallium/targets/pipe-loader/pipe_radeonsi.c:38:33: fatal error: radeonsi/si_driinfo.h: No such file or directory #include "radeonsi/si_driinfo.h" ^ compilation terminated. Makefile:994: recipe for target 'pipe_radeonsi.lo' failed make[4]: *** [pipe_radeonsi.lo] Error 1 Trivial. Fixes: 0f8c5de8690e7c ("radeonsi: prepare for driver-specific driconf options")
* clover: Fix build after llvm r309911Jan Vesely2017-08-032-1/+7
| | | | | Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* radeonsi: program tile swizzle for color and FMASK surfaces for GFX & SDMAMarek Olšák2017-08-045-4/+33
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: if FMASK is disabled, set CB_COLORi_FMASK = CB_COLORi_BASE properlyMarek Olšák2017-08-041-1/+5
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: reallocate textures with non-zero tile_swizzle on exportMarek Olšák2017-08-041-1/+3
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: enable computation of tile swizzleMarek Olšák2017-08-042-1/+13
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: align DCC size for surfaces that use tile swizzleMarek Olšák2017-08-041-2/+9
| | | | | | | | Note that dcc_alignment = pipe_interleave_bytes * num_pipes * num_banks, which is greater than the previous open-coded alignment. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: limit tile swizzle to non-mipmaps on SIMarek Olšák2017-08-041-1/+3
| | | | | | | Mipmapping with tile swizzle doesn't work. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: enable tile swizzle for mipmapped texturesMarek Olšák2017-08-041-34/+46
| | | | | | | | | | | The tile swizzle computation was done after the whole miptree was computed, but that was too late, because at that point AddrSurfInfoOut contained information about the smallest miplevel, which is never 2D-tiled. The correct way is to do the computation before the second level is computed. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: set structure size and handle errors for AddrComputeBaseSwizzleMarek Olšák2017-08-041-1/+8
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: increment surf_index only when tile swizzle is allowedMarek Olšák2017-08-044-4/+7
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: compute tile swizzle only when it's allowedMarek Olšák2017-08-041-2/+4
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: add RADEON_SURF_SHAREABLEMarek Olšák2017-08-042-1/+4
| | | | | | | Shareable textures won't use tile swizzle. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: remove RADEON_SURF_HAS_TILE_MODE_INDEXMarek Olšák2017-08-043-5/+0
| | | | | | | it's useless Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: move tile_swizzle to ac_surface and document itMarek Olšák2017-08-044-8/+25
| | | | | | | Gfx9 will use it too. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: fix handling of NumSamples=1 (v2)Brian Paul2017-08-033-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Mesa we use the convention that if gl_renderbuffer::NumSamples or gl_texture_image::NumSamples is zero, it's a non-MSAA surface. Otherwise, it's an MSAA surface. But in gallium nr_samples=1 is a non-MSAA surface. Before, if the user called glRenderbufferStorageMultisample() or glTexImage2DMultisample() with samples=1 we skipped the search for the next higher number of supported samples and asked the gallium driver to create a surface with nr_samples=1. So we got a non-MSAA surface. This failed to meet the expection of the user making those calls. This patch changes the sample count checks in st_AllocTextureStorage() and st_renderbuffer_alloc_storage() to test for samples > 0 instead of > 1. And we now start querying for MSAA support at samples=2 since gallium has no concept of a 1x MSAA surface. A specific example of this problem is the Piglit arb_framebuffer_srgb-blit test. It calls glRenderbufferStorageMultisample() with samples=1 to request an MSAA renderbuffer with the minimum supported number of MSAA samples. Instead of creating a 4x or 8x, etc. MSAA surface, we wound up creating a non-MSAA surface. Finally, add a comment on the gl_renderbuffer::NumSamples field. There is one piglit regression with the VMware driver: ext_framebuffer_multisample-blit-mismatched-formats fails because now we're actually creating 4x MSAA surfaces (the requested sample count is 1) and we're hitting some sort of bug in the blitter code. That will have to be fixed separately. Other drivers may find regressions too now that MSAA surfaces are really being created. v2: start quering for MSAA support with samples=2 instead of 1. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/docs: add more info about TXF and MSAA texturesBrian Paul2017-08-031-1/+3
| | | | | | | If the texture is multisampled, the coord.w component indicates which sample to fetch. Reviewed-by: Roland Scheidegger <[email protected]>
* st/mesa: minor clean-ups in st_atom_msaa.cBrian Paul2017-08-031-16/+18
| | | | | Whitespace, formatting, combine nr_bits assignment with declaration. Trivial.
* gallium/docs: document automatic per-sample FS executionBrian Paul2017-08-031-0/+6
| | | | | | | | | Both the GLSL 4.00 specs and DX10.1 specs specify that if a fragment shader uses the sample ID or sample position inputs, the shader is automatically run at per sample frequency. Document that expectation for gallium fragment shaders. Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: init more msaa fieldsBrian Paul2017-08-031-0/+2
| | | | | | | | | | | The default values for GL_SAMPLE_SHADING and GL_MIN_SAMPLE_SHADING_VALUE are missing from the state tables in the GL spec, but they're supposed to be GL_FALSE and 0.0, per the GL_ARB_sample_shading spec. Add code for that, just to be explicit. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* swr: Add arch flags to support Cray and PGI compilersChuck Atkins2017-08-031-4/+4
| | | | | | | | | | Note that the Cray flags (-target-cpu=) need to come first since the cray programming environment uses wappers around other compilers. By checking the wrapper flags first, you can be sure to match the wrapper flag instead of the underlying compiler (gcc, intel, pgi, etc.) flags. Signed-off-by: Chuck Atkins <[email protected]> Reviewed-by: Tim Rowley <[email protected]>
* st/osmesa: add osmesa framebuffer iface hash table per st managerBruce Cherniak2017-08-031-0/+11
| | | | | | | | | | | | | Commit bbc29393d3 didn't include osmesa state_tracker. This patch adds necessary initialization. Fixes crash in OSMesa initialization. Created-by: Charmaine Lee <[email protected]> Tested-by: Bruce Cherniak <[email protected]> Reviewed-by: Charmaine Lee <[email protected]> Cc: 17.2 <[email protected]>
* anv: put anv_extensions.c in gitignoreLionel Landwerlin2017-08-031-0/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* pipe-loader: fix build of dynamic pipe-driversNicolai Hähnle2017-08-035-4/+7
| | | | | | | | | | | | | v2: add libxmlconfig.la to the dynamic pipe_radeonsi driver v3: add libxmlconfig.la to targets/opencl build v4: add EXPAT_LIBS to opencl build (note: for only-opencl builds, Emil's configure.ac changes are also needed) Fixes: bc7f41e11d3 ("gallium: add pipe_screen_config to screen_create functions") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102014 Tested-by: Andy Furniss <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (v1)
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