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* radeonsi/gfx10: mask DCC tile swizzle by alignmentNicolai Hähnle2019-07-032-2/+7
* radeonsi/gfx10: implement hardware MSAA resolveNicolai Hähnle2019-07-035-2/+17
* radeonsi/gfx10: fix binding on si_update_scratch_relocsNicolai Hähnle2019-07-031-3/+7
* radeonsi/gfx10: set llvm_has_working_vgpr_indexingNicolai Hähnle2019-07-031-3/+2
* radeonsi/gfx10: implement load_const_buffer_desc_fast_pathNicolai Hähnle2019-07-031-7/+14
* radeonsi/gfx10: take PRIMID from the correct output when exported by GSNicolai Hähnle2019-07-031-2/+2
* radeonsi/gfx10: change location of instance ID shader inputNicolai Hähnle2019-07-031-2/+11
* radeonsi/gfx10: set USER_DATA_ADDR offset for geometry shadersNicolai Hähnle2019-07-031-2/+8
* radeonsi/gfx10: implement si_emit_derived_tess_stateNicolai Hähnle2019-07-031-2/+6
* radeonsi/gfx10: implement si_shader_gsNicolai Hähnle2019-07-031-15/+29
* radeonsi/gfx10: implement preload_ring_buffersNicolai Hähnle2019-07-031-11/+20
* radeonsi/gfx10: implement si_set_ring_bufferNicolai Hähnle2019-07-031-2/+9
* radeonsi/gfx10: allow rectangle outputs from NGG primitive shaderNicolai Hähnle2019-07-031-0/+1
* radeonsi/gfx10: emit VGT_GS_OUT_PRIM_TYPE from draw and add it to VS_STATENicolai Hähnle2019-07-035-48/+52
* radeonsi/gfx10: NGG geometry shader PM4 and uploadNicolai Hähnle2019-07-035-29/+316
* radeonsi/gfx10: generate geometry shaders for NGGNicolai Hähnle2019-07-034-4/+439
* radeonsi/gfx10: use the correct register for image descriptor dumpingNicolai Hähnle2019-07-031-3/+5
* radeonsi/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy modeNicolai Hähnle2019-07-031-7/+60
* radeonsi/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSETNicolai Hähnle2019-07-031-1/+5
* radeonsi/gfx10: setup registers for OpenGL computeNicolai Hähnle2019-07-031-2/+11
* radeonsi/gfx10: set user data base registersNicolai Hähnle2019-07-031-8/+32
* radeonsi/gfx10: implement gfx10_shader_nggNicolai Hähnle2019-07-034-1/+211
* radeonsi/gfx10: add NGG registers to si_init_configNicolai Hähnle2019-07-031-0/+15
* radeonsi/gfx10: update shader-related fields in si_init_configNicolai Hähnle2019-07-031-7/+17
* radeonsi/gfx10: implement si_shader_psNicolai Hähnle2019-07-031-7/+13
* radeonsi/gfx10: generate VS and TES as NGG merged ESGS shadersNicolai Hähnle2019-07-036-25/+382
* radeonsi/gfx10: distinguish between merged shaders and multi-part shadersNicolai Hähnle2019-07-031-3/+10
* radeonsi/gfx10: update si_get_shader_nameNicolai Hähnle2019-07-031-0/+4
* radeonsi/gfx10: add as_ngg shader key bitNicolai Hähnle2019-07-033-10/+42
* radeonsi/gfx10: implement si_update_shadersNicolai Hähnle2019-07-031-50/+62
* radeonsi/gfx10: implement si_build_vgt_shader_configNicolai Hähnle2019-07-032-2/+14
* radeonsi/gfx10: keep track of whether NGG is usedNicolai Hähnle2019-07-034-1/+31
* radeonsi/gfx10: document NGG shader stagesNicolai Hähnle2019-07-031-10/+15
* radeonsi/gfx10: implement gfx10_emit_cache_flushNicolai Hähnle2019-07-034-3/+195
* radeonsi/gfx10: add si_context::emit_cache_flushNicolai Hähnle2019-07-039-9/+15
* radeonsi/gfx10: implement DB registersNicolai Hähnle2019-07-033-13/+56
* radeonsi/gfx10: set CB registersNicolai Hähnle2019-07-032-5/+76
* radeonsi/gfx10: always set up sample locationsNicolai Hähnle2019-07-031-1/+5
* radeonsi/gfx10: use Z32_FLOAT_CLAMP for upgraded depth texturesNicolai Hähnle2019-07-032-10/+22
* radeonsi/gfx10: implement vertex format changesNicolai Hähnle2019-07-032-6/+23
* radeonsi/gfx10: implement si_set_{constant,shader}_bufferNicolai Hähnle2019-07-031-6/+20
* radeonsi/gfx10: implement si_make_buffer_descriptorNicolai Hähnle2019-07-031-10/+28
* radeonsi/gfx10: implement si_set_mutable_tex_desc_fieldsNicolai Hähnle2019-07-031-5/+30
* radeonsi/gfx10: gfx10 can render up to 8192 layersNicolai Hähnle2019-07-031-0/+4
* radeonsi/gfx10: add gfx10_make_texture_descriptorNicolai Hähnle2019-07-031-1/+187
* radeonsi/gfx10: add pipe_screen::make_texture_descriptorNicolai Hähnle2019-07-035-16/+19
* radeonsi/gfx10: determine view->is_integer based on the pipe_formatNicolai Hähnle2019-07-031-6/+15
* radeonsi/gfx10: implement si_is_format_supportedNicolai Hähnle2019-07-031-0/+17
* radeonsi/gfx10: generate gfx10_format_table.hNicolai Hähnle2019-07-035-2/+300
* radeonsi/gfx10: set MAX_ALLOC_COUNTNicolai Hähnle2019-07-031-2/+14
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 04:19:18 +0000