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* radv: only use VkSamplerCreateInfo::compareOp if enabledSamuel Pitoiset2020-01-151-1/+5
| | | | | | | | | Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2350 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3392> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3392>
* v3d: fix bug when checking result of syncobj fence importIago Toral Quiroga2020-01-151-1/+1
| | | | | | Reviewed-by: Alejandro Piñeiro <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383>
* st/mesa: run st_nir_lower_tex_src_plane for lowered xyuv/ayuvJonathan Marek2020-01-151-1/+2
| | | | | | | | | Has the effect of removing the nir_tex_src_plane for these formats too. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>
* st/mesa: don't lower YUV when driver supports it nativelyJonathan Marek2020-01-156-55/+82
| | | | | | | | | | This fixes YUYV support on etnaviv. Fixes: 7404833c "gallium: add handling for YUV planar surfaces" Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>
* radv: Disable VK_EXT_sample_locations on GFX10.Bas Nieuwenhuizen2020-01-151-1/+2
| | | | | | | | | Workaround for https://gitlab.freedesktop.org/mesa/mesa/issues/2163 CC: <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3236> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3236>
* st/mesa: implement EGLImageTargetTexStorageGurchetan Singh2020-01-152-0/+30
| | | | | | | | We can now support this extension. Acked-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
* st/mesa: refactor egl image binding a bitGurchetan Singh2020-01-151-2/+3
| | | | | | | We'll need it for egl image tex storage. Acked-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
* st/dri: track if image is created by a dmabufGurchetan Singh2020-01-154-0/+12
| | | | | | | Will be used by EXT_EGL_image_storage later. Acked-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
* freedreno/ir3: rename instructionsRob Clark2020-01-157-14/+25
| | | | | | | | | | | | | Turns out this range of opcodes are more general purpose if/else/endif instructions. We should re-work tess to create a basic block and use normal flow control. And possibly (for a6xx+) optimize cases to use if/else/endif when appropriate. Signed-off-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398>
* nir/algebraic: sqrt(x)*sqrt(x) -> fabs(x)Elie Tournier2020-01-151-0/+1
| | | | | | | | | | | | | | | | | total instructions in shared programs: 12840840 -> 12839341 (-0.01%) instructions in affected programs: 122581 -> 121082 (-1.22%) helped: 559 HURT: 0 total cycles in shared programs: 302505756 -> 302490031 (<.01%) cycles in affected programs: 2022900 -> 2007175 (-0.78%) helped: 1090 HURT: 130 Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Matt Turner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>
* nir/algebraic: i2f(f2i()) -> trunc()Elie Tournier2020-01-151-0/+5
| | | | | | | | | | | | | | | | total instructions in shared programs: 12840968 -> 12840784 (<.01%) instructions in affected programs: 17886 -> 17702 (-1.03%) helped: 77 HURT: 0 total cycles in shared programs: 302508917 -> 302505592 (<.01%) cycles in affected programs: 249964 -> 246639 (-1.33%) helped: 70 HURT: 7 Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>
* i965: Reuse the new core glsl_count_dword_slots().Eric Anholt2020-01-143-55/+3
| | | | | | | | | The only difference I could see was treating interfaces like structs. Maintain that case. Reviewed-by: Kristian H. Kristensen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
* mesa/st: Move the dword slot counting function to glsl_types as well.Eric Anholt2020-01-1411-130/+75
| | | | | | | | | | | | | To implement NIR-to-TGSI, we need to be able to get the size of the uniform variable for the TGSI declaration, not just the .driver_location. With its location in mesa/st, drivers couldn't link to it from nir-to-tgsi. This feels like a common enough function to want, so let's share it in the core compiler. Reviewed-by: Kristian H. Kristensen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
* mesa/prog: Reuse count_vec4_slots() from ir_to_mesa.Eric Anholt2020-01-141-75/+1
| | | | | Reviewed-by: Kristian H. Kristensen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
* mesa/st: Move the vec4 type size function into core GLSL types.Eric Anholt2020-01-148-109/+45
| | | | | | | | | | The only bit that gallium varied on was handling of bindless. We can retain previous behavior for count_attribute_slots() by passing in "true" (though I suspect this is just giving a silly answer to a silly question), and delete our recursive function from mesa/st. Reviewed-by: Kristian H. Kristensen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
* mesa/st: Deduplicate the NIR uniform lowering code.Eric Anholt2020-01-143-18/+16
| | | | | | | Just a little refactor as I go looking at the type size functions. Reviewed-by: Kristian H. Kristensen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
* radeonsi: move PS LLVM code into si_shader_llvm_ps.cMarek Olšák2020-01-147-1283/+1317
| | | | | | | | This is an attempt to clean up si_shader.c. v2: don't move code that is not specific to LLVM Reviewed-by: Timothy Arceri <[email protected]> (v1)
* radeonsi: remove always constant ballot_mask_bits from si_llvm_context_initMarek Olšák2020-01-143-10/+6
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: fold si_create_function into si_llvm_create_funcMarek Olšák2020-01-144-43/+30
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_shader_create -> si_create_shader_variant for clarityMarek Olšák2020-01-144-8/+10
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_compile_tgsi_main -> si_build_main_functionMarek Olšák2020-01-141-5/+5
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: clean up si_shader_infoMarek Olšák2020-01-143-131/+45
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: merge si_tessctrl_info into si_shader_infoMarek Olšák2020-01-144-23/+10
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: fork tgsi_shader_info and tgsi_tessctrl_infoMarek Olšák2020-01-1412-56/+205
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_shader_info -> si_shader_binary_infoMarek Olšák2020-01-141-2/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: remove TGSI from commentsMarek Olšák2020-01-144-11/+9
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: rename DBG_NO_TGSI -> DBG_NO_NIRMarek Olšák2020-01-143-3/+3
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: don't adjust depth and stencil PS output locationsMarek Olšák2020-01-142-11/+3
| | | | | | this was for compatibility with TGSI Reviewed-by: Timothy Arceri <[email protected]>
* nir: Add missing nir_var_mem_global to various passesCaio Marcelo de Oliveira Filho2020-01-144-16/+28
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
* spirv: Handle PhysicalStorageBuffer in memory barriersCaio Marcelo de Oliveira Filho2020-01-141-2/+6
| | | | | | | | | | | | | PhysicalStorageBuffer is lowered to nir_var_mem_global, and SPIR-V 1.5rev1 in section "3.25. Memory Semantics <id>" says UniformMemory Apply the memory-ordering constraints to StorageBuffer, PhysicalStorageBuffer, or Uniform Storage Class memory. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
* spirv: Drop EXT for PhysicalStorageBuffer symbolsCaio Marcelo de Oliveira Filho2020-01-142-11/+11
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
* aco: Flip s_cbranch / s_cselect to optimize out an s_not if possible.Timur Kristóf2020-01-142-8/+51
| | | | | | | | | | | | | | | | | | | | | When possible, get rid of an s_not when all it does is invert the SCC, and its successor s_cbranch / s_cselect can be inverted instead. Also modify some parts of instruction_selection to take advantage of this feature. Example: s2: %3900, s1: %3899:scc = s_andn2_b64 %0:exec, %406 s2: %3902 = s_cselect_b64 -1, 0, %3900:scc s2: %407, s1: %3903:scc = s_not_b64 %3902 s2: %3906, s1: %3905:scc = s_and_b64 %407, %0:exec p_cbranch_z %3905:scc Can now be optimized to: s2: %3900, s1: %3899:scc = s_andn2_b64 %0:exec, %406 p_cbranch_nz %3900:scc Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Optimize out s_and with exec, when used on uniform bitwise values.Timur Kristóf2020-01-141-4/+31
| | | | | | | | | | | | | Previously all booleans needed an s_and with exec when they were turned into a scalar condition. However, this is not needed for uniform booleans. v2 by Daniel Schürmann: - Make the code more readable v3 by Timur Kristóf: - Fix regressions, make it work in wave32 mode Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Don't skip combine_instruction when definitions[1] is used.Timur Kristóf2020-01-141-1/+1
| | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Allow optimizing vote_all and nir_op_iand.Timur Kristóf2020-01-141-6/+6
| | | | | | | | | By adding an extra instruction, we can replace the operands of the s_cselect_b64, which allows it to get picked up by the optimizer when it looks for uniform booleans. Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Implement 64-bit constant propagation.Timur Kristóf2020-01-144-25/+58
| | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* panfrost: Fix linear depth texturesAlyssa Rosenzweig2020-01-146-31/+53
| | | | | | | | | | | | | | | | As pointed out by Boris, what we were calling PAN_LINEAR depth textures was in fact u-interleaved tiled (!), but we never noticed since we flipped the flag used for sampling, leading to all sorts of fun bugs when attempting to directly acess depth textures from the CPU. Which begs the question -- if what we called LINEAR was tiled, how do we actually render linear depth textures? It turns out the flags for AFBC form a mali_block_format 2-bit code just like their render-target counterparts, so we can render to any of the above. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reported-by: Boris Brezillon <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393>
* vulkan/wsi: Add a driconf option to force WSI to advertise BGRA8_UNORM firstJason Ekstrand2020-01-149-8/+85
| | | | | | | | | | | The Aztec Ruins benchmark just grabs the first format in the list and SRGB causes it to render washed out. With this workaround, it renders the same as OpenGL. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350>
* intel/fs: Only use SLM fence in compute shadersCaio Marcelo de Oliveira Filho2020-01-141-0/+3
| | | | | | | Fixes: b390ff35170 ("intel/fs: Add support for SLM fence in Gen11") Fixes: e142061399c ("intel/fs: Implement scoped_memory_barrier") Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: actually enable VBOs in user SGPRsMarek Olšák2020-01-141-1/+1
| | | | | Fixes: 363b4027fcb - radeonsi: put up to 5 VBO descriptors into user SGPRs Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: fix assertion and other failures in si_emit_graphics_shader_pointersMarek Olšák2020-01-141-3/+4
| | | | | | | The assertion was failing. Fixes: 363b4027fcb - radeonsi: put up to 5 VBO descriptors into user SGPRs Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* nir/algebraic: a & ~(a >> 31) -> imax(a, 0)Rhys Perry2020-01-141-0/+1
| | | | | | | | | | | | | | | | | | Found in some Doom shaders Totals from affected shaders: SGPRS: 30056 -> 30064 (0.03 %) VGPRS: 28024 -> 28024 (0.00 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Code Size: 4278648 -> 4270852 (-0.18 %) bytes Max Waves: 1476 -> 1476 (0.00 %) Instructions: 835287 -> 833338 (-0.23 %) Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3089> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3089>
* etnaviv: Fix assert when try to accumulate an invalid fdMarco Felsch2020-01-141-1/+2
| | | | | | | | | | Check if it is a valid fd before merging it to the context's fd. Signed-off-by: Marco Felsch <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381>
* pan/midgard: Fix midgard_compile.h includesAfonso Bordado2020-01-141-0/+1
| | | | | | | We now use enum mali_format which is defined in panfrost-job.h Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3243> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3243>
* anv: only use VkSamplerCreateInfo::compareOp if enabledLionel Landwerlin2020-01-141-1/+3
| | | | | | | | | | | | | | | The spec says nothing about the validity of the compareOp field when compareEnable is false. v2: use vulkan enum to pick default value (Caio) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2350 Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3387> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3387>
* nir/sink,nir/move: move/sink nir_op_movRhys Perry2020-01-142-0/+6
| | | | | | | | | | | | | | | | Can uncover opportunities to move other instructions. This can increase register usage, but that doesn't seem to actually happen. This optimizes a pattern of a load_per_vertex_input followed by several moves and then a store_output in a different block. v2: add nir_move_copies to make it optional Signed-off-by: Rhys Perry <[email protected]> Acked-by: Jason Ekstrand <[email protected]> (v1) Acked-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2420> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2420>
* nir/sink,nir/move: move/sink load_per_vertex_inputRhys Perry2020-01-141-1/+2
| | | | | | | Signed-off-by: Rhys Perry <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2420>
* gitlab-ci: Consolidate container and build stages for LAVATomeu Vizoso2020-01-149-321/+203
| | | | | | | | | | | | | | | | Use the normal build job to also prepare the artifacts for LAVA jobs. For that, the build container needs to also build the test suites, kernel, ramdisk, etc. Then the build job will place the just-built Mesa in the ramdisk and the test job can generate a LAVA job and point to those artifacts. Signed-off-by: Tomeu Vizoso <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3295> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3295>
* aco: add integer min/max to can_swap_operandsRhys Perry2020-01-141-0/+4
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
* aco: improve readfirstlane after uniform LDS loadsRhys Perry2020-01-141-2/+5
| | | | | | | | | | | | | | Totals from affected shaders: SGPRS: 976 -> 968 (-0.82 %) VGPRS: 580 -> 584 (0.69 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Code Size: 106032 -> 103076 (-2.79 %) bytes Max Waves: 237 -> 237 (0.00 %) Instructions: 19452 -> 18740 (-3.66 %) Signed-off-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 21:40:55 +0000