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* nine: Don't reference the dead TGSI_OPCODE_NRM.Jose Fonseca2014-11-241-1/+1
| | | | | | | | | | The translation is lowering it to not using TGSI_OPCODE_NRM, anyway. v2: Extracted from a larger patch by Jose that also dropped DP2A usage. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Axel Davy <[email protected]> Reviewed-by: David Heidelberg <[email protected]>
* nine: Don't use the otherwise-dead SFL opcode in an unreachable path.Eric Anholt2014-11-241-1/+1
| | | | | | Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Axel Davy <[email protected]> Reviewed-by: David Heidelberg <[email protected]>
* i965/gen6/gs: Don't declare a src_reg with struct.Matt Turner2014-11-241-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Fix all32h/any32h predicate disassembly.Matt Turner2014-11-241-1/+1
| | | | Reviewed-by: Chris Forbes <[email protected]>
* glsl: Fix tautological comparison.Matt Turner2014-11-241-1/+1
| | | | | | | | | | | | Caught by clang. warning: comparison of constant -1 with expression of type 'ir_texture_opcode' is always false [-Wtautological-constant-out-of-range-compare] if (op == -1) ~~ ^ ~~ Reviewed-by: Kenneth Graunke <[email protected]>
* util: Prefer atomic intrinsics to inline assembly.Matt Turner2014-11-241-2/+2
| | | | | | | | | | | | | Cuts a little more than 1k of .text size from i915g. This was previously done in commit 5f66b340 and subsequently reverted in commit 3661f757 after bug 30514 was filed. I believe the cause of bug 30514 wasn't anything related to cross compiling, but rather that the toolchain used defaulted to -march=i386, and i386 doesn't have the CMPXCHG or XADD instructions used to implement the intrinsics. So we reverted a patch that improved things so that we didn't break compilation for a platform that never could have worked anyway.
* util: Implement assume() for clang.Matt Turner2014-11-241-1/+11
| | | | Reviewed-by: Jordan Justen <[email protected]>
* i965: Don't overwrite the math function with conditional mod.Matt Turner2014-11-242-2/+4
| | | | | | | | | | | | | | | Ben was asking about the undocumented restriction that the math instruction cannot use the dependency control hints. I went to reconfirm and disabled the is_math() check in opt_set_dependency_control() and saw that the disassembled math instructions with dependency hints had a bogus math function. We were mistakenly overwriting it by setting an empty conditional mod. Unfortunately, this wasn't the cause of the aforementioned problem (I reproduced it). This bug is benign, since we don't set dependeny hints on math instructions -- but maybe some day. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Assert that math instructions don't have conditional mod.Matt Turner2014-11-242-0/+4
| | | | | | The math function field is at the same location as conditional mod. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Remove unused ast copy constructors.Matt Turner2014-11-241-29/+0
| | | | | | | | | These were added in commits a760c738 and 43757135 to be used in implementing C-style aggregate initializers (commit 1b0d6aef). Paul rewrote that code in commit 0da1a2cc to use GLSL types, rather than AST types, leaving these copy constructors unused. Tested by making them private and providing no definition.
* glapi: Remove dead gl_offsets.py.Matt Turner2014-11-241-120/+0
| | | | Dead since commit 07b85457.
* glapi: Remove dead extension_helper.py.Matt Turner2014-11-242-326/+0
| | | | Dead since commit 3d16088f.
* vc4: Fix some inconsistent indentation.Eric Anholt2014-11-241-6/+6
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* vc4: Don't forget to actually connect the fence code.Eric Anholt2014-11-241-0/+2
| | | | I thought I'd tested this.
* vc4: Add a note about a piece of errata I've learned about.Eric Anholt2014-11-241-0/+4
| | | | | Right now in my environment I've only got a small CMA area, so this constraint ends up holding.
* mesa: Fix Get(GL_TRANSPOSE_CURRENT_MATRIX_ARB) to transposeChris Forbes2014-11-241-1/+1
| | | | | | | | | This was just returning the same value as GL_CURRENT_MATRIX_ARB. Spotted while investigating something else in apitrace. Signed-off-by: Chris Forbes <[email protected]> Cc: "10.3 10.4" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Generate unique names for each const array lowered to uniformscros-mesa-10.3-r29-vanillacros-mesa-10.3-r28-vanillacros-mesa-10.3-r15-vanillacros-mesa-10.3-r13-vanillachadv/cros-mesa-10.3-r29-vanillachadv/cros-mesa-10.3-r28-vanillachadv/cros-mesa-10.3-r15-vanillachadv/cros-mesa-10.3-r13-vanillaChris Forbes2014-11-241-1/+5
| | | | | | | | | | | Uniform names (even for hidden uniforms) are required to be unique; some parts of the compiler assume they can be looked up by name. Fixes the piglit test: tests/spec/glsl-1.20/linker/array-initializers-1 Signed-off-by: Chris Forbes <[email protected]> Cc: "10.4" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Handle nested uniform array indexingChris Forbes2014-11-241-29/+37
| | | | | | | | | | | | | | | | | | | When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <[email protected]> Cc: "10.3 10.4" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r600g: do all CUBE ALU operations before gradient texture operations (v2.1)Dave Airlie2014-11-241-64/+72
| | | | | | | | | | | | | This moves all the CUBE section above the gradients section, so that the gradient emission happens on one block which is what sb/hardware expect. v2: avoid changes to bytecode by using spare temps v2.1: shame gcc, oh the shame. (uninit var warnings) Cc: "10.4 10.3" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: fix texture gradients instruction emission (v2)Dave Airlie2014-11-241-28/+31
| | | | | | | | | | | | | | | | | | | The piglit tests were failing, and it appeared to be SB optimising out things, but Glenn pointed out the gradients are meant to be clause local, so we should emit the texture instructions in the same clause. This moves things around to always copy to a temp and then emit the texture clauses for H/V. v2: Glenn pointed out we could get another ALU fetch in the wrong place, so load the src gpr earlier as well. Fixes at least: ./bin/tex-miplevel-selection textureGrad 2D Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.4 10.3" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50,nvc0: buffer resources can be bound as other things down the lineIlia Mirkin2014-11-232-14/+14
| | | | | | | | | res->bind is not an indicator of how the resource is currently bound. buffers can be rebound across different binding points without changing underlying storage. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.3" <[email protected]>
* nv50,nvc0: actually check constbufs for invalidationIlia Mirkin2014-11-232-3/+6
| | | | | | | | The number of vertex buffers has nothing to do with the number of bound constbufs. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.3" <[email protected]>
* nv50/ir: set neg modifiers on min/max argsIlia Mirkin2014-11-231-0/+2
| | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=86618 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.3" <[email protected]>
* mesa: Fix function name in GetActiveUniformName errorChris Forbes2014-11-231-1/+1
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i915g: Fallback copy_render for ZS formatsStéphane Marchesin2014-11-221-1/+11
| | | | | | | These don't work out of the box, need more work, maybe with a proxy format? Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Add back 4444 and 5551 formatsStéphane Marchesin2014-11-222-2/+4
| | | | | | Now that we have the transfers working, we can re-add those formats. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Don't limit blitter to POT texturesStéphane Marchesin2014-11-221-3/+2
| | | | | | | Now that we have NPOT support for u_blitter, there is no reason to limit this any longer. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Align all texture dimensions to the next POTStéphane Marchesin2014-11-221-28/+29
| | | | | | | | This creates a usable layout for all NPOT textures. Of course these still have lots of limitations, but at least we can render to a level. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Fix typosStéphane Marchesin2014-11-221-2/+2
| | | | Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Fix maxlod computation.Stéphane Marchesin2014-11-221-3/+3
| | | | Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Fix offset for level != 0Stéphane Marchesin2014-11-225-8/+27
| | | | | | | | For NPOT texture layouts, we want to be able to access texture levels other than 0 directly. Since the hw doesn't support that, We do it by adding the offset directly. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Don't write constants past I915_MAX_CONSTANTStéphane Marchesin2014-11-221-1/+1
| | | | | | | | This happens with glsl-convolution-1, where we have 64 constants. This doesn't make the test pass (we don't have 64 constants anyway, only 32) but this prevents it from crashing. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Don't hardcode array size for phase countStéphane Marchesin2014-11-221-1/+1
| | | | | | This is an array of temp registers, so use I915_MAX_TEMPORARY for the size. Signed-off-by: Stéphane Marchesin <[email protected]>
* draw: allow LLVM use on non-SSE2 X86 cpusDavid Heidelberg2014-11-221-14/+1
| | | | | | | | | | | | | | | | This patch remove workaround related to LLVM < 3.2 bug. Original bug has been closed as fixed in 2011. At this moment gallium requires LLVM 3.3 (2013). LLVM has been tested without SSE2 support in commit ca70de9bd20bc4a11b2d2d368e0cc1f49527a947 and removed after requiring LLVM 3.3 in commit 013ff2fae13da41c2f5619c4698b0a7b5aa6a06d Original LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=6960 Signed-off-by: David Heidelberg <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* docs: add news item and link release notes for mesa 10.3.4Emil Velikov2014-11-222-0/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: Add sha256 sums for the 10.3.4 releaseEmil Velikov2014-11-221-1/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 72c27d7a3acc40b8a77a277f7cd975fb8e60dca5)
* Add release notes for the 10.3.4 releaseEmil Velikov2014-11-221-0/+104
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 26c8ecd85dade7be5759c4de0b3916fbc186dc43)
* i965: Make Gen4-5 push constants call _mesa_load_state_parameters too.Kenneth Graunke2014-11-211-0/+4
| | | | | | | | | | | | | | | | | | In commit 5e37a2a4a8a, I made the pull constant code stop calling _mesa_load_state_parameters() when there were no pull parameters. This worked fine on Gen6+ because the push constant code also called it if there were any push constants. However, the Gen4-5 push constant code wasn't doing this. This patch makes it do so, like the Gen6+ code. A better long term solution would be to make core Mesa just handle this for us when necessary. Fixes around 8766 Piglit tests on Ironlake, and probably Gen4 as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Tested-by: Mark Janes <[email protected]>
* i965/vec4/gen8: Handle the MUL dest hazard exceptionBen Widawsky2014-11-212-2/+19
| | | | | | | | | | | Fix one of the few cases where we can't reliable touch the destination hazard bits. I am explicitly doing this patch individually so it is easy to backport. I was tempted to do this patch before the previous patch which reorganized the code, but I believe even doing that first, this is still easy to backport. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212 Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Extract depctrl hazardsBen Widawsky2014-11-211-22/+27
| | | | | | | | | | | | | | | | | Move this to a separate function so that we can begin to add other little caveats without making too big a mess. NOTE: There is some desire to improve this function eventually, but we need to fix a bug first. v2: Use const for the inst for the hazard check (Matt) Invert safe logic to get rid of the double negative (Matt) Add PRM reference for predicates (Matt) Add note about empirical evidence for math (Matt) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove is_valid_3src().Matt Turner2014-11-213-8/+1
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Remove is_valid_3src() checks from emit_lrp.Matt Turner2014-11-211-4/+1
| | | | | | | The visitor emits MOVs to temporary registers for immediates, so these never trigger. For further proof, check case ir_triop_fma. Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Remove unused apply_stride().Matt Turner2014-11-212-11/+0
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Move ip_record class to its one use.Matt Turner2014-11-212-12/+12
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* i965: Move common fields into backend_instruction.Matt Turner2014-11-213-5/+2
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Combine offset/texture_offset fields.Matt Turner2014-11-216-15/+13
| | | | | | | | texture_offset was only used by some texturing operations, and offset was only used by spill/unspill and some URB operations. These fields are never used at the same time. Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: use minnum and maxnum LLVM intrinsics for MIN and MAX opcodesMarek Olšák2014-11-211-0/+7
| | | | | | | So far it has been compiled into pretty ugly code (8 instructions or so for either opcode). Reviewed-by: Tom Stellard <[email protected]>
* vc4: Update for new kernel ABI with async execution and waits.Eric Anholt2014-11-209-3/+250
| | | | | Our submits now return immediately and you have to manually wait for things to complete if you want to (like a normal driver).
* i915: Only use TEXCOORDTYPE_VECTOR with cube maps on gen2Ville Syrjälä2014-11-201-18/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check that the target is GL_TEXTURE_CUBE_MAP before emitting TEXCOORDTYPE_VECTOR texture coordinates. I'm not sure if the hardware would like CARTESIAN coordinates with cube maps, and as I'm too lazy to find out just emit the VECTOR coordinates for cube maps always. For other targets use CARTESIAN or HOMOGENOUS depending on the number of texture coordinates provided. Fixes rendering of the "electric" background texture in chromium-bsu main menu. We appear to be provided with three texture coordinates there (I'm guessing due to the funky texture matrix rotation it does). So the code would decide to use TEXCOORDTYPE_VECTOR instead of TEXCOORDTYPE_CARTESIAN even though we're dealing with a 2D texure. The results weren't what one might expect. demos/cubemap still works, which hopefully indicates that this doesn't break things. Also tested with: bin/glean -o -v -v -v -t +texCube --quick bin/cubemap -auto from piglit. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i965/disasm: Properly decode branch_ctrl (gen8+)Ben Widawsky2014-11-203-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for decoding the new branch control bit. I saw two things wrong with the existing code. 1. It didn't bother trying to decode the bit. - While we do not *intentionally* emit this bit today, I think it's interesting to see if we somehow ended up with the bit set. It may also be useful in the future. 2. It seemed to be the wrong bit. - The docs are pretty poor wrt which bit this actually occupies. To me, it /looks/ like it should be bit 28. I am not sure where Ken got 30 from. I verified it should be 28 by looking at the simulator code. I also added the most basic support for GOTO simply so we don't need to remember to change the function in the future. v2: Move the branch_ctrl check out of the if gen >= 6 check to make it more readable. (Matt) ENDIF doesn't have branch_ctrl (Matt + Ken) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
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