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* mesa: android has no log2f nor ffsChia-I Wu2011-08-211-1/+7
| | | | | | Define log2f(v) to be logf(v) / M_LN2 and ffs to __builtin_ffs. Reviewed-by: Chad Versace <[email protected]>
* ralloc: include limits.h for SIZE_MAX on AndroidChia-I Wu2011-08-211-0/+5
| | | | | | | Android does not define SIZE_MAX in stdint.h. We have to include limits.h for it. Reviewed-by: Chad Versace <[email protected]>
* gallium: add PIPE_OS_ANDROID supportChia-I Wu2011-08-214-2/+22
| | | | | | | Android uses Linux kernel and its own C runtime. It resembles PIPE_OS_LINUX a lot with some minor exceptions. Reviewed-by: Brian Paul <[email protected]>
* glsl: remove an unnecessary header includeChia-I Wu2011-08-211-1/+0
| | | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* mesa: fix !FEATURE_GL buildChia-I Wu2011-08-211-18/+18
| | | | | | | Move vbo_exec_FlushVertices_internal out of FEATURE_beginend. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.Kenneth Graunke2011-08-201-0/+3
| | | | | | | Makes the new vertex shader backend work on Ivybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Don't double-convert integer/boolean uniforms.Kenneth Graunke2011-08-191-16/+20
| | | | | | | | | | | | | When ctx->Const.NativeIntegers is set, Core Mesa loads integer/boolean uniforms directly, rather than loading the floating point equivalent. So, when that's set, we don't need to perform any conversions. Unfortunately, we can't properly support native integers with the old vertex shader backend, so this patch leaves them disabled for now. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa, glsl_to_tgsi: Add new gl_context::NativeIntegers flag.Kenneth Graunke2011-08-193-27/+37
| | | | | | | | | | | | | | | | | | | Previously, native integer support was based on whether the driver advertised GLSL 1.30 or not. However, drivers that natively support integers may wish to do so for older GLSL versions as well. Adding this new opt-in flag allows them to do so. Currently disabled by default on all drivers, which was the existing behavior (no drivers currently implement GLSL 1.30). Fixes piglit tests on i965 with INTEL_GLSL_VERSION=130 set: - spec/glsl-1.10/fs-uniform-int-110.shader_test - spec/glsl-1.30/fs-uniform-int-130.shader_test (it was doubly converting the data) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Remove incorrect usage of the 'struct' keyword on classes.Kenneth Graunke2011-08-191-2/+2
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965/fs: Change incorrect use of 'struct fs_reg' to simply 'fs_reg'.Kenneth Graunke2011-08-191-1/+1
| | | | | | It's actually a class. Signed-off-by: Kenneth Graunke <[email protected]>
* glsl: Remove unused variable.Kenneth Graunke2011-08-191-1/+0
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* i965/vs: Implement proper register allocation instead of 1:1 mapping.Eric Anholt2011-08-192-1/+155
| | | | | | Fixes vs-atan-* and several others. This is not the real solution we eventually want, which will pack floats, vec2s, and vec3s into vec4 registers, but this code should provide the framework for that.
* i965/vs: Add simple dead code elimination.Eric Anholt2011-08-193-0/+38
| | | | | This is copied right from the fragment shader. It is needed for real register allocation to work correctly.
* i965/vs: Copy the live intervals calculation over from the FS.Eric Anholt2011-08-194-0/+139
| | | | | | This is a rather pessimistic calculation, since it doesn't distinguish individual channels of a vec4, or elements of an array, but should be a minimum start for register allocation.
* i965/vs: Remove stale comment about compressed instructions.Eric Anholt2011-08-191-1/+0
| | | | | This was copy'n'paste from the fragment shader, and didn't make sense here.
* r600g: don't allocate separate depth and stencil for transfer textures on EGMarek Olšák2011-08-191-1/+2
| | | | | | | | The state tracker expects depth and stencil pixels interleaved. Evergreen can bind an interleaved depth-stencil resource as a colorbuffer, but not as a zbuffer. The hardware can do the interleaving for us when decompressing.
* r600g: finally enable float depth buffers on evergreenMarek Olšák2011-08-191-0/+11
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* r600g: rename resource -> view in create_sampler_viewMarek Olšák2011-08-192-32/+26
| | | | | The sampler view is not a resource. Also remove the unused desc variable.
* r600g: hack around a problem with texture alignmentMarek Olšák2011-08-191-0/+10
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* r600g: simplify the conditionals determining array modeMarek Olšák2011-08-191-20/+11
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* r600g: put depth and stencil into one backing bufferMarek Olšák2011-08-191-10/+17
| | | | For DRI2 sharing.
* r600g: fix depth-stencil on evergreenMarek Olšák2011-08-194-55/+99
| | | | | | | | | | | | | | Such that it actually works in apps which use both. A separate buffer is allocated for stencil. The only exception is the window-system-provided depth-stencil buffer, where depth and stencil share the same buffer. This fixes: - fbo-depthstencil-GL_DEPTH24_STENCIL8-clear - fbo-depthstencil-GL_DEPTH24_STENCIL8-drawpixels-FLOAT-and-USHORT - fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-24_8 - fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-FLOAT-and-USHORT
* mesa: handle array textures in GenerateMipmap(), FramebufferTexture1/2D()Brian Paul2011-08-191-3/+21
| | | | | | | | | This was an unfinished to-do item before. With this patch and the two preceeding patches, piglit's fbo-generatemipmap-array test runs and passes instead of generating a GL error and dying on an assertion. Reviewed-by: Ian Romanick <[email protected]>
* meta: use fallback mipmap generation for 1D/2D texture arraysBrian Paul2011-08-191-2/+5
| | | | | | | We could do 1D/2D arrays with textured quad rendering, but it'll take some work (as with 3D textures). Reviewed-by: Ian Romanick <[email protected]>
* mesa: set Q=1 for OPCODE_TEX executionBrian Paul2011-08-191-0/+8
| | | | | | | | | | | Q should not be significant for OPCODE_TEX, but it winds up getting passed to the compute_lambda() function. Make sure it's 1.0 to prevent garbage values, which is effectively what we get when the swizzle is coord.xyzz (which is what GLSL gives us). Part of the fix for piglit's fbo-generatemipmap-array test. Reviewed-by: Ian Romanick <[email protected]>
* mesa: restructure error checking in _mesa_FramebufferTexture1D/2DEXT()Brian Paul2011-08-191-11/+45
| | | | | | In anticipation of adding more texture targets. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Declare _mesa_meta_begin()/end() as publicChad Versace2011-08-192-142/+147
| | | | | | | | | | | Declare _mesa_meta_begin()/end() in meta.h so that drivers can write custom meta-ops (such as HiZ resolves for i965). This necessitates moving the the META_* macros into meta.h. To prevent naming collisions, this commit renames each macro to be MESA_META_*. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* nv50: fix potential null deref in insn modifer optimization passChristoph Bumiller2011-08-191-2/+4
| | | | Bug introduced in 34980cd153050111edc545545ddff11f5b68347e.
* glx: use a block to fix declarations after code warningBrian Paul2011-08-191-7/+9
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* r600g: fix a possible crash in r600_adjust_gprsMarek Olšák2011-08-191-1/+1
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* mesa: fix incorrect error code in _mesa_FramebufferTexture1D/3DEXT()Brian Paul2011-08-181-2/+2
| | | | | The spec says GL_INVALID_OPERATION is generated when texture!=0 and textarget is not a legal value. We had this right for the 2D function.
* glapi: update .gitignore for generated ES dispatch headersPaul Berry2011-08-182-3/+4
| | | | | | | | | | | Commit 6eff33dc (glapi: generate ES dispatch headers from core mesa) replaced the autogenerated files src/mapi/es1api/main/{dispatch,remap_helper}.h with new autogenerated files src/mesa/main/api_exec_es{1,2}_{dispatch,remap_helper}.h. This patch updates the .gitignore files to properly ignore the new autogenerated files, and stop ignoring the old autogenerated files. Reviewed-by: Chia-I Wu <[email protected]>
* llvmpipe: Don't build lp_test_arit on MSVC.José Fonseca2011-08-181-1/+1
| | | | | Several issues due to expf/logf/etc either not being declared, or being defined as a macro.
* llvmpipe: snprintf->util_snprintf.José Fonseca2011-08-181-1/+2
| | | | For MSVC.
* llvmpipe: Add u_math.h include.José Fonseca2011-08-181-0/+1
| | | | Necessary on platforms with incomplete math.h
* scons: Add support for LLVM-2.9 on Windows.José Fonseca2011-08-181-1/+15
| | | | MinGW & MSVC, although I've only tested the former.
* glx: Don't flush twice if we fallback to dri2CopySubBufferKristian Høgsberg2011-08-181-11/+10
| | | | | | | The flush extensions flush call indicates end of frame and should only be called once per frame. However, in the dri2SwapBuffer fallback path, we call flush and then call dri2CopySubBuffer, which also calls flush. Refactor the code to only call flush once.
* r600g: implement NV_primitive_restart functionality (v2)Marek Olšák2011-08-184-1/+11
| | | | | | | | | Needed for GL3. v2: evergreen support I don't set PA_SU_SC_MODE_CNTL.MULTI_PRIM_IB_ENA. piglit/primitive-restart does pass though. Tested on RV730 and EG-REDWOOD.
* r600g: fix scons buildMarek Olšák2011-08-171-0/+1
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* i965/fs: Fix 32-bit integer multiplication.Eric Anholt2011-08-172-1/+22
| | | | | | | | | The MUL opcode does a 16bit * 32bit multiply, and we need to do the MACH to get the top 16bit * 32bit added in. Fixes fs-op-mult-int-*, fs-op-mult-ivec* Reviewed-by: Kenneth Graunke <[email protected]>
* nv50: don't drop flags definition when merging SAT with ADD/MADChristoph Bumiller2011-08-171-0/+2
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* st/mesa: fix incorrect loop over instruction src regsBrian Paul2011-08-171-1/+1
| | | | The array of src regs is of size 3, not 4.
* st/dri: Indent driconf optionsLauri Kasanen2011-08-171-7/+11
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* xmlpool.h: fix a typoLauri Kasanen2011-08-171-1/+1
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* xmlconfig: Make the error message more informativeLauri Kasanen2011-08-171-1/+1
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* mesa: Bump instruction execution limit to 65536Ian Romanick2011-08-161-1/+1
| | | | | | | | | | | Shader Model 3.0[1] requires that shaders be able to execute at least 65536 instructions. Bump Mesa maxExec to that limit. This allows several vertex shaders in the OpenGL ES 2.0 conformance test suite to run to completion. 1: http://en.wikipedia.org/wiki/High_Level_Shader_Language Reviewed-by: Eric Anholt <[email protected]>
* mesa: Add partial constant propagation pass for Mesa IRIan Romanick2011-08-165-0/+458
| | | | | | | | | | | | This cleans up some code generated by the IR-to-Mesa pass for i915. In particular, some shaders involving arrays of constant matrices result in really bad code. v2: Silence several warnings from merging the gl_constant_value work. Fix DP[23] folding. Add support for a bunch more opcodes that appear in piglit runs on i915. Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Emit a MAD(b, -a, b) for !a && bIan Romanick2011-08-161-0/+52
| | | | | | | | !a && b occurs frequently when nexted if-statements have been flattened. It should also be possible use a MAD for (a && b) || c, though that would require a MAD_SAT. Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Implement ir_binop_all_equal using DP4 w/SGEIan Romanick2011-08-161-1/+12
| | | | | | | | | | | | | | | | | | | The operation ir_binop_all_equal is !(a.x != b.x || a.y != b.y || a.z != b.z || a.w != b.w). Logical-or is implemented using addition (followed by clampling to [0,1]) on values of 0.0 and 1.0. Replacing the logical-or operators with addition gives !bool((int(a.x != b.x) + int(a.y == b.y) + int(a.z == b.z) + int(a.w == b.w)). This can be implemented using a dot-product with a vector of all 1.0. After the dot-product, the value will be an integer on the range [0,4]. Previously a SEQ instruction was used to clamp the resulting logic value to [0,1] and invert the result. Using an SGE instruction on the negation of the dot-product result has the same effect. Many older shader architectures do not support the SEQ instruction. It must be emulated using two SGE instructions and a MUL. On these architectures, the single SGE saves two instructions. Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Implement ir_binop_any_nequal using DP4 w/saturate or DP4 w/SLTIan Romanick2011-08-161-2/+20
| | | | | | | | | The operation ir_binop_any_nequal is (a.x != b.x) || (a.y != b.y) || (a.z != b.z) || (a.w != b.w), and that is the same as any(bvec4(a.x != b.x, a.y != b.y, a.z != b.z, a.w != b.w)). Implement the any() part the same way the regular ir_unop_any is implemented. Reviewed-by: Eric Anholt <[email protected]>
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