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* radv: Improve fence signalling in QueueSubmit.Bas Nieuwenhuizen2019-10-301-13/+24
* radv: Do sparse binding in queue submission.Bas Nieuwenhuizen2019-10-301-60/+81
* radv: Split out commandbuffer submission.Bas Nieuwenhuizen2019-10-301-163/+187
* radv: Clean up unused variable.Bas Nieuwenhuizen2019-10-301-4/+3
* radv: Add an early exit in the secure compile if we already have the cache en...Bas Nieuwenhuizen2019-10-301-0/+14
* radv: Compute hashes in secure process for secure compilation.Bas Nieuwenhuizen2019-10-301-0/+23
* zink: drop nop descriptor-updatesErik Faye-Lund2019-10-301-4/+5
* zink: use bitfield for dirty flaggingErik Faye-Lund2019-10-302-7/+6
* zink: use dynamic state for line-widthErik Faye-Lund2019-10-305-13/+17
* zink: Use optimal layout instead of general. Reduces valid layer warnings. Fi...Duncan Hopkins2019-10-303-36/+113
* gitlab-ci: Disable meson-windows job for the time beingMichel Dänzer2019-10-301-1/+1
* radv: make use of radv_sc_read()Timothy Arceri2019-10-303-39/+76
* radv: add radv_sc_read() helperTimothy Arceri2019-10-302-0/+42
* radv: allow select() calls in secure compileTimothy Arceri2019-10-301-1/+5
* mapi: Improve the x86 tsd stubs performance.Lepton Wu2019-10-291-5/+6
* mapi: Inline call x86_current_tls.Lepton Wu2019-10-291-4/+8
* mapi: Clean up entry_patch_public for x86 tlsLepton Wu2019-10-291-10/+7
* mapi: split entry_generate_or_patch for x86 tlsLepton Wu2019-10-291-5/+16
* mapi: Adapted libglvnd x86 tsd changesJonathan Gray2019-10-291-5/+11
* spirv: Don't fail if multiple ordering semantics bits are setCaio Marcelo de Oliveira Filho2019-10-291-9/+30
* intel/isl: Allow stencil buffer to support compression on Gen12+Sagar Ghuge2019-10-291-2/+3
* iris: Resolve stencil resource prior to copy or used by CPUSagar Ghuge2019-10-291-9/+19
* iris: Prepare resources before stencil blit operationSagar Ghuge2019-10-291-7/+52
* iris: Prepare depth resource if clear_depth enableSagar Ghuge2019-10-291-2/+2
* iris: Prepare stencil resource before clear depth stencilSagar Ghuge2019-10-291-2/+10
* iris: Resolve stencil buffer lossless compression with WM_HZ_OP packetSagar Ghuge2019-10-291-9/+13
* intel/blorp: Set stencil resolve enable bitSagar Ghuge2019-10-291-4/+17
* intel: Track stencil aux usage on Gen12+Sagar Ghuge2019-10-294-0/+10
* intel/blorp: Add helper function for stencil buffer resolveSagar Ghuge2019-10-292-0/+34
* intel/blorp: Assign correct view while clearing depth stencilSagar Ghuge2019-10-291-1/+1
* genxml/gen12: Add Stencil Buffer Resolve Enable bitSagar Ghuge2019-10-291-0/+1
* iris: Allocate main and aux surfaces togetherNanley Chery2019-10-291-34/+21
* iris: Determine aux offsets within configure_auxNanley Chery2019-10-291-10/+9
* iris: Bail resource creation upon aux creation errorNanley Chery2019-10-291-16/+17
* iris: Drop iris_resource::aux::extra_aux::boNanley Chery2019-10-292-16/+3
* zink: pass line width from rast_state to gfx_pipeline_state.Duncan Hopkins2019-10-291-1/+3
* anv: Reduce the minimum number of relocationsJason Ekstrand2019-10-291-1/+1
* anv: Delay allocation of relocation listsJason Ekstrand2019-10-291-67/+71
* anv: Implement new way for setting streamout buffers.Plamena Manolova2019-10-293-0/+19
* iris: Implement new way for setting streamout buffers.Plamena Manolova2019-10-292-3/+23
* genxml: Add 3DSTATE_SO_BUFFER_INDEX_* instructionsPlamena Manolova2019-10-291-0/+47
* freedreno/a6xx: add a618 supportRob Clark2019-10-293-0/+27
* freedreno/a6xx: cleanup magic registersRob Clark2019-10-296-22/+47
* freedreno/a6xx: remove some left over dead codeRob Clark2019-10-291-10/+0
* anv: Set depthBounds to true in anv_GetPhysicalDeviceFeatures.Plamena Manolova2019-10-291-1/+1
* genxml: Change 3DSTATE_DEPTH_BOUNDS bias.Plamena Manolova2019-10-291-1/+1
* gitlab-ci: Only run the pipeline if any files affecting it have changedMichel Dänzer2019-10-291-3/+21
* gallium/swr: Enable GL_ARB_gpu_shader5: multiple streamsKrzysztof Raszkowski2019-10-296-14/+78
* panfrost: Remove unused definitions in mali-job.hAlyssa Rosenzweig2019-10-291-9/+1
* panfrost: Cleanup _shader_upper -> shaderAlyssa Rosenzweig2019-10-293-17/+14
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