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* intel/mi: Add gen_mi_nz() and gen_mi_z() helpers.Kenneth Graunke2019-07-251-0/+20
| | | | | | These provide comparisons against zero. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/mi: Add a gen_mi_ior() to go with gen_mi_iand()Kenneth Graunke2019-07-251-0/+8
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/mi: Optimize away LOAD_REGISTER_REG from a register to itselfKenneth Graunke2019-07-251-3/+5
| | | | | | | | We might want to resolve something to be in a particular register, so we can access it outside of the gen_mi framework...but it may already be in that register, at which point there's no work to do. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: Make iris_query.c a genxml-compiled file.Kenneth Graunke2019-07-256-65/+48
| | | | | | This will let us use Jason's new MI-builder shortly. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: Move iris_resolve_conditional_render to the vtable.Kenneth Graunke2019-07-253-5/+8
| | | | | | It's going to be in genxml code shortly. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: Refactor genxml macros and inlines into iris_genx_macros.h.Kenneth Graunke2019-07-254-73/+125
| | | | | | | This will let us put the genxml boilerplate in one place, before we expand genxml to more files shortly. Like i965/genX_boilerplate.h. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: Make an iris_genx_protos.h header for prototypes.Kenneth Graunke2019-07-254-28/+74
| | | | | | | This lets us specify the prototypes once, instead of cut and pasting them per generation. isl uses a similar approach (isl_genX_priv.h). Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* radeonsi: fix DAL hang due to incorrect DCC offset on RavenMarek Olšák2019-07-251-1/+22
| | | | | | Set the correct relative offset. Fixes: f8b6c5a "radeonsi: rewrite si_get_opaque_metadata, also for gfx10 support"
* anv: Disable subgroup arithmetic on gen7Jason Ekstrand2019-07-251-3/+10
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* gitlab-ci: Add a shader-db run using v3d on drm-shim.Eric Anholt2019-07-254-2/+36
| | | | | | | | | | | | | | This provides significant compiler coverage during CI at a fairly low cost in CPU time (~17s per thread for 4 threads on gst-gitlab-htz-runner3). I'm leaving wget in the docker image, as once this is in master I'm planning on having an automatic shader-db comparison between master and the branch included in the artifacts. I also haven't done freedreno yet, because it has some races when run in multithreaded mode that I'm still tracking down. Reviewed-by: Eric Engestrom <[email protected]>
* gitlab-ci: Only keep the build logs as artifacts.Eric Anholt2019-07-251-2/+5
| | | | | | | | | | | On a build failure, we were tarring up the whole ccache directory, build.ninja, build products, etc. This was over 400MB compressed on a recent early meson-main build failure, which fd.o then has to hang on to for 4 weeks. The build logs are probably the interesting part, are potentially useful regardless ("how did CI's build flags differ from mine?"), and are <500k uncompressed on my personal meson build. Reviewed-by: Michel Dänzer <[email protected]>
* gitlab-ci: Always set libdir to lib/Eric Anholt2019-07-252-1/+1
| | | | | | | | I introduced libdir for cross-builds so we could point at the resulting drivers without per-arch dependencies, but I'd rather not have to type x86_64-linux-whatever for non-cross-builds either. Reviewed-by: Eric Engestrom <[email protected]>
* freedreno: Add support for drm-shim.Eric Anholt2019-07-256-0/+229
| | | | | | I'm using this for shader-db analysis on x86_64 systems. Reviewed-by: Rob Clark <[email protected]>
* v3d: Introduce a DRM shim for calling out to the simulator.Eric Anholt2019-07-2515-2/+1815
| | | | | | | | | | | | The goal is to enable testing of parts of drivers without depending on any particular kernel version or hardware being present. Simply set LD_PRELOAD=$PREFIX/lib/libv3d_drm_shim.so in your environment, and we'll fake a /dev/dri/renderD128 (or whatever the next available node is) using v3dv3. That node can then be used with the surfaceless or gbm EGL platforms. Acked-by: Iago Toral Quiroga <[email protected]>
* glsl: report no function instead of empty candidate listErik Faye-Lund2019-07-251-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When generating the error message for a missing function error where all available overloads were missing due to a too low GLSL version, we used to report something like this: ---8<--- 0:224(14): error: no matching function for call to `textureCubeLod(samplerCube, vec3, float)'; candidates are: 0:224(14): error: type mismatch ---8<--- This is a pretty confusing error message, and can throw people off when debugging. So let's instead check if any overload is available before we decide what to print. This allow us to report something like this instead: ---8<--- 0:224(14): error: no function with name 'textureCubeLod' 0:224(14): error: type mismatch ---8<--- This is arguably easier to understand for programmers, and doesn't send you on a wild goose chase to figure out what argument is wrong just because you stopped reading the message prematurely. I'm of course referring to a friend, not me. For sure. I would never do that. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* radv: Set correct metadata size for GFX9+.Bas Nieuwenhuizen2019-07-251-1/+2
| | | | | | | | | | | Without correct size, radeonsi assumes the metadata is incorrect, which can and will cause issues. Since the metadata is really incorrect without the size, let us fix that. Fixes: e43cc3e3afc "radv/gfx9: handle GFX9 opaque metadata" Reviewed-by: Samuel Pitoiset <[email protected]>
* anv: report HOST_ALLOCATION as supported for imagesArcady Goldmints-Orlov2019-07-251-0/+4
| | | | | | | | | | Report VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT as supported for images. It was being shown supported for buffers, but not images. Fixes: 69cc6272fbc1 ("anv: Implement VK_EXT_external_memory_host") Reviewed-by: Lionel Landwerlin <[email protected]>
* radv/gfx10: fix intensity formats by setting ALPHA_IS_ON_MSBSamuel Pitoiset2019-07-251-6/+11
| | | | | | | | | | This fixes dEQP-VK.rasterization.primitive_size.points.point_size_* This also fixes some black squares with the Sascha SSAO demo. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: use L2 for DMA copy/fill operationsSamuel Pitoiset2019-07-251-0/+16
| | | | | | | | | | | | | It's coherent and faster. GFX7-GFX9 should also support this but for now only uses L2 for GFX10 because it's untested on previous gens. This fixes dEQP-VK.memory.pipeline_barrier.transfer_* This also fixes some missing geometry in Dawn Of War III because VBOs weren't updated correctly. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* pan/midgard: Optimize varying projectionAlyssa Rosenzweig2019-07-255-14/+114
| | | | | | | | | | | | | | | | | | | | | | | | We add a new opt pass fusing perspective projection with varyings. Minor win..? We don't combine non-varying projections, since if we're too agressive, the extra load/store traffic will hurt us so it's not really a win in practice. total instructions in shared programs: 3915 -> 3913 (-0.05%) instructions in affected programs: 76 -> 74 (-2.63%) helped: 1 HURT: 0 total bundles in shared programs: 2520 -> 2519 (-0.04%) bundles in affected programs: 46 -> 45 (-2.17%) helped: 1 HURT: 0 total quadwords in shared programs: 4027 -> 4025 (-0.05%) quadwords in affected programs: 80 -> 78 (-2.50%) helped: 1 HURT: 0 Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add perspective projection recombine passAlyssa Rosenzweig2019-07-253-0/+117
| | | | | | | | We don't use it yet, since it's actually a shader-db regression. This is primarily helpful as an intermediate step for attaching projection to varyings. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Force perspective ops to use vec4Alyssa Rosenzweig2019-07-251-0/+16
| | | | | | It doesn't make sense to use them with anything less. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add R27-only op handlingAlyssa Rosenzweig2019-07-252-11/+48
| | | | | | We use a special conflicting register class. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add OP_R27_ONLY helperAlyssa Rosenzweig2019-07-251-0/+5
| | | | | | | | While load/store ops like st_vary can take an argument in either r26/r27, ops like those for perspective projection must specifically take their argument in r27. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Enable RA for st_varyAlyssa Rosenzweig2019-07-251-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that all the piping is in place to do so without regressions, we flip on automatic register allocation for varyings. Hooray! total instructions in shared programs: 4025 -> 3915 (-2.73%) instructions in affected programs: 1667 -> 1557 (-6.60%) helped: 62 HURT: 0 helped stats (abs) min: 1 max: 3 x̄: 1.77 x̃: 2 helped stats (rel) min: 0.93% max: 20.00% x̄: 10.80% x̃: 10.64% 95% mean confidence interval for instructions value: -1.89 -1.66 95% mean confidence interval for instructions %-change: -12.50% -9.11% Instructions are helped. total bundles in shared programs: 2683 -> 2520 (-6.08%) bundles in affected programs: 1066 -> 903 (-15.29%) helped: 62 HURT: 0 helped stats (abs) min: 1 max: 3 x̄: 2.63 x̃: 3 helped stats (rel) min: 2.94% max: 42.86% x̄: 23.85% x̃: 22.50% 95% mean confidence interval for bundles value: -2.83 -2.43 95% mean confidence interval for bundles %-change: -27.73% -19.97% Bundles are helped. total quadwords in shared programs: 4192 -> 4027 (-3.94%) quadwords in affected programs: 1584 -> 1419 (-10.42%) helped: 62 HURT: 0 helped stats (abs) min: 1 max: 4 x̄: 2.66 x̃: 3 helped stats (rel) min: 1.85% max: 30.00% x̄: 16.49% x̃: 16.52% 95% mean confidence interval for quadwords value: -2.87 -2.46 95% mean confidence interval for quadwords %-change: -19.14% -13.84% Quadwords are helped. total registers in shared programs: 433 -> 411 (-5.08%) registers in affected programs: 67 -> 45 (-32.84%) helped: 23 HURT: 1 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 25.00% max: 50.00% x̄: 41.30% x̃: 50.00% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 14.29% max: 14.29% x̄: 14.29% x̃: 14.29% 95% mean confidence interval for registers value: -1.09 -0.74 95% mean confidence interval for registers %-change: -45.45% -32.52% Registers are helped. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Remove check for `class`Alyssa Rosenzweig2019-07-251-1/+0
| | | | | | Fixes classes defaulting to vec4 in some cases. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Move uniforms to special registersAlyssa Rosenzweig2019-07-253-2/+25
| | | | | | | The load/store pipes can't take a uniform register in, so an explicit move is necessary here. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Emit st_vary registers in install_registersAlyssa Rosenzweig2019-07-251-3/+11
| | | | | | Now that we have its registers handled normally like the rest of the IR. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_lower_special_reads helperAlyssa Rosenzweig2019-07-253-0/+117
| | | | | | | | Given the constraints on special registers, we add a helper for lowering these by inserting moves (copies) where needed to satsify the ISA constraints. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add emit_explicit_constant helperAlyssa Rosenzweig2019-07-251-10/+16
| | | | | | | We generalize the constant emission helper used in fragment writeout as we'll also need it for vertex outputs. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_rewrite_index_src_tagAlyssa Rosenzweig2019-07-252-0/+14
| | | | | | | Specialized version of a rewrite that only rewrites a certain type of instruction. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add class checkAlyssa Rosenzweig2019-07-251-1/+30
| | | | | | | | | | | This ensures the rules for accessing special register classes are satisfied. This is asserted as a prepass should have lowered offending uses to something satisfying these rules. Special register classes are *not* work registers and cannot be used for RMW operations; they are essentially 1-way pipes straight into/from fixed-function logic in the shader cores. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Implement class spillingAlyssa Rosenzweig2019-07-251-14/+39
| | | | | | | | We reuse the same register spilling mechanism as for work->memory to spill special->work registers, e.g. to allow writing out more than 2 vec4 varyings (without better scheduling anyway). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extend liveness analysis to st_varyAlyssa Rosenzweig2019-07-251-8/+1
| | | | | | These can consume sources now. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Implement load/store register classingAlyssa Rosenzweig2019-07-251-17/+70
| | | | | | | | This does not yet support special->work spilling, nor does it support multiclass breakup. These corner cases will be handled in succeeding commits. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Allocate special register classesAlyssa Rosenzweig2019-07-253-39/+57
| | | | | | | We'll want to also handle load/store and texture registers in our RA loop. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Move copy propagation into its own fileAlyssa Rosenzweig2019-07-255-83/+120
| | | | | | We also expose some utilities it uses as general MIR helpers. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_simple_swizzle helperAlyssa Rosenzweig2019-07-251-0/+15
| | | | | | | Checks for x/xy/xyz/xyzw style swizzles (slightly more general but you get the idea). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_single_use helperAlyssa Rosenzweig2019-07-252-0/+22
| | | | | | Helps as an optimization heuristic. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Compute I/O counts from shader_infoAlyssa Rosenzweig2019-07-253-9/+14
| | | | | | ...rather than exposing it in the vendored compiler region. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Don't DIY point size/coord fieldsAlyssa Rosenzweig2019-07-252-9/+2
| | | | | | Again, it's in shader_info for us! Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use nir_gather_info information about discardsAlyssa Rosenzweig2019-07-254-9/+1
| | | | | | No need to track this ourselves! Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use NIR helper invocations infoAlyssa Rosenzweig2019-07-253-1/+5
| | | | | | | We don't need to guesstimate this ourselves. This will help when we bringup derivatives. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/sfbd: Flesh out fragment jobAlyssa Rosenzweig2019-07-251-13/+35
| | | | | | | | We include a zsbuf attachment function based on how the corresponding MFBD code works, as well as extending cbufs to mipmapped rendering while we're at it. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Disable tiled formats on SFBD systemsAlyssa Rosenzweig2019-07-251-1/+3
| | | | | | Just because we don't have the format codes to render to them yet. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Move require_sfbd to screenAlyssa Rosenzweig2019-07-256-15/+18
| | | | | | We'll need it to specialize resource creation by chip. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Reserve, but do not upload, shader paddingAlyssa Rosenzweig2019-07-251-3/+3
| | | | | | Fixes invalid read errors reported by valgrind. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* util/ra: Add a getter for a node classAlyssa Rosenzweig2019-07-252-0/+8
| | | | | | | | Complements the existing getters and the setter for node class. To be used in the Panfrost RA refactor. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* panfrost/ci: Update kernel to 5.2Tomeu Vizoso2019-07-252-3/+3
| | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* egl: Also query modifiers when exporting DMABufNicolas Dufresne2019-07-251-4/+22
| | | | | | | | | | | This fixes eglExportDMABUFImageQueryMESA() so it will report the modififers of the underlying image. Without this information, re-importing will likely be broken as it is rare these days that no modifiers are used. Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Fixes: 8f7338f284cdb1fef64c ("egl: add initial EGL_MESA_image_dma_buf_export v2.4")
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