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* i965/disasm: Rename msg_target to SFID.Kenneth Graunke2014-06-301-12/+8
| | | | | | | | | | We haven't used the name "message target" in a while - there are a lot of things called "target", and it gets confusing. SFID ("Shared Function ID") is the term commonly used in the modern documentation. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Fix typo in RT UNORM write message.Kenneth Graunke2014-06-301-1/+1
| | | | | | | | | The name of this message is "Render Target UNORM Write" (Sandybridge PRM, Volume 4 Part 1, Page 210). Drop the bogus 'c'. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Use Gen6+ SFID case labels.Kenneth Graunke2014-06-301-2/+4
| | | | | | | | | | Most developers will recognize the Gen6+ SFID names more quickly than the Gen4-5 ones. Given that they're the same values, just use the new names. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: "Handle" Gen8+ HF/DF immediate cases.Kenneth Graunke2014-06-301-0/+7
| | | | | | | | | | | We should print something properly, but I'm not sure how to properly print an HF, and we don't have any DFs today to test with. This is at least better than the current Gen8 disassembler, which would simply assert fail. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Cut piles of duplicate swizzle printing.Kenneth Graunke2014-06-301-89/+26
| | | | | | | | Making a helper function saves us from cut and pasting this four times. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly decode negate source modifiers on Broadwell.Kenneth Graunke2014-06-301-4/+49
| | | | | | | | | This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da to brw_disasm.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Improve disassembly of atomic messages on Haswell+.Kenneth Graunke2014-06-301-7/+21
| | | | | | | | | | This backports the atomic message disassembly support from gen8_disasm.c, which additionally offers support for decoding atomic surface read/write messages, and showing SIMD modes and other details. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Actually disassemble Gen7+ URB opcodes.Kenneth Graunke2014-06-301-3/+19
| | | | | | | | | | | I never bothered implementing the disassembler for Gen7+ URB opcodes, so we were just disassembling them as Ironlake/Sandybridge ones. This looked pretty bad when running Paul's GS EndPrimitive tests, as the "write OWord" message was decoded at ff_sync, which doesn't exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Decode Broadwell's invm/rsqrtm math functions.Kenneth Graunke2014-06-301-0/+2
| | | | | | | | We don't use these yet, but we may as well disassemble them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.Kenneth Graunke2014-06-301-2/+3
| | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble all32h/any32h align1 predicates.Kenneth Graunke2014-06-301-11/+13
| | | | | | | | | While we're adding things, use symbolic constants rather than magic numbers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add #defines for any32h/all32h predication.Kenneth Graunke2014-06-301-0/+2
| | | | | | | | | | These have existed since Ivybridge. We don't use them today, but the Gen8+ disassembler supports them, and I'd like to use symbolic names rather than magic numbers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Mark ELSE as having UIP on Gen8+.Kenneth Graunke2014-06-301-0/+1
| | | | | | | | | This makes brw_disasm.c able to disassemble ELSE instructions correctly on Broadwell. (gen8_disasm.c already handles this correctly.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble jump targets on Gen4-5.Kenneth Graunke2014-06-301-0/+15
| | | | | | | | | | | | | | | | | | | Previously, our dissasembly for flow control instructions looked like: 0x00000040: else(8) ip 65540D { align16 switch }; It didn't print InstCount properly for ELSE/ENDIF, and didn't even attempt to disassemble PopCount. Now it looks like: 0x00000040: else(8) Jump: 4 Pop: 1 { align16 switch }; which is much more readable. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Improve disassembly of jump targets on Gen6+.Kenneth Graunke2014-06-301-18/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, flow control instructions generated output like: (+f0) if(8) 12 8 null 0x000c0008UD { align16 WE_normal 1Q }; which included a dissasembly of the register fields, even though those are meaningless for flow control instructions---those bits are reused for another purpose. It also wasn't immediately obvious which number was UIP and which was JIP. With this patch, we instead output: (+f0) if(8) JIP: 8 UIP: 12 { align16 WE_normal 1Q }; which is much clearer. The patch also introduces has_uip/has_jip helper functions which clear up a some generation/opcode checking mess. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Add support for new Gen8+ register types.Kenneth Graunke2014-06-301-16/+24
| | | | | | | | | While we're at it, use proper names rather than magic numbers for the existing fields. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Restyle brw_disasm.c.Kenneth Graunke2014-06-301-1234/+1231
| | | | | | | | | | | | | | | | | | | | brw_disasm.c basically wasn't following the Mesa coding style at all. It used 4-space indent instead of 3-space, didn't cuddle braces, didn't put function return types on a separate line, put extra spaces in function calls (between the name and parenthesis), and a number of other things. This made it fairly obnoxious to work on, since my editor is configured to follow Mesa style in the Mesa source repository. Fixing it to follow a consistent style now should save time dealing with it later. These modifications were originally generated by: $ indent -br -i3 -npcs -ce -cs -l80 --no-tabs with some manual changes afterwards to fit our style better. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Create an "opcode" temporary.Kenneth Graunke2014-06-301-31/+30
| | | | | | | | This saves typing brw_inst_opcode(brw, inst) everywhere. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Eliminate opcode pointer.Kenneth Graunke2014-06-301-8/+7
| | | | | | | | | opcode is just a pointer to opcode_descs; we may as well use that directly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* Remove the ATI_envmap_bumpmap extensionJason Ekstrand2014-06-3032-860/+8
| | | | | | | | | | | As far as I can tell, the Intel mesa driver is the only driver in the world still supporting this legacy extension. If someone wants to do bump mapping, they can use shaders. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> [v1] Reviewed-by: Chris Forbes <[email protected]> [v2] Reviewed-by: Ian Romanick <[email protected]> [v3]
* meta: Use AMD_vertex_shader_layer instead of a GS for layered clears.Kenneth Graunke2014-06-301-37/+16
| | | | | | | | | | | | | | | | | | | | | | | On i965, enabling and disabling the GS is not free: you have to do a full pipeline stall, reconfigure the URB and push constant space, and emit a bunch of state. Most clears aren't layered, so the GS isn't needed in the common case. But we turned it on universally. Using AMD_vertex_shader_layer allows us to skip setting up the GS altogether, while achieving the same effect. According to Ilia, current nVidia GPUs can't do AMD_vertex_shader_layer. However, since nouveau is Gallium-based, they're unlikely to ever care about this path. Intel and AMD GPUs both support the extension. Since i965 is the only driver using this path which does layered rendering, we may as well target it at that. v2: Improve commit message. No code changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* docs: mark "Geometry shader multiple streams" as done for i965Samuel Iglesias Gonsalvez2014-06-301-1/+1
| | | | | Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Enable vertex streams up to MAX_VERTEX_STREAMS.Iago Toral Quiroga2014-06-301-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: Enable simultaneous queries on different streams.Iago Toral Quiroga2014-06-302-10/+11
| | | | | | | | It should be possible to query the number of primitives written to each individual stream by a geometry shader in a single draw call. For that we need to have up to MAX_VERTEX_STREAM separate query objects. Reviewed-by: Ian Romanick <[email protected]>
* i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.Iago Toral Quiroga2014-06-302-7/+26
| | | | | | | | | | | | | | | | | So far we have been using CL_INVOCATION_COUNT to resolve this query but this is no good with streams, as only stream 0 reaches the clipping stage. Instead we will use SO_PRIM_STORAGE_NEEDED which can keep track of the primitives sent to each individual stream. Since SO_PRIM_STORAGE_NEEDED is related to the SOL stage and according to ARB_transform_feedback3 we need to be able to query primitives generated in each stream whether transform feedback is active or not what we do is to enable the SOL unit even if transform feedback is not active but disable all output buffers in that case. This effectively disables transform feedback but permits activation of statistics enabling SO_PRIM_STORAGE_NEEDED even when transform feedback is not active. Reviewed-by: Chris Forbes <[email protected]>
* i965: Implement GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN with non-zero streams.Iago Toral Quiroga2014-06-301-4/+4
| | | | Reviewed-by: Chris Forbes <[email protected]>
* mesa: Include stream information in indexed queries.Iago Toral Quiroga2014-06-302-0/+2
| | | | Reviewed-by: Ian Romanick <[email protected]>
* glsl: include streamId when reading/printing ir_variable IR.Samuel Iglesias Gonsalvez2014-06-302-2/+11
| | | | | | Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: include streamId when reading/printing emit-vertex and end-primitive IR.Iago Toral Quiroga2014-06-302-8/+27
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965/gs: Set control data bits for vertices emitted in stream mode.Iago Toral Quiroga2014-06-302-1/+51
| | | | | | | In stream mode we have to set control data bits with the StreamID information for every vertex. Reviewed-by: Chris Forbes <[email protected]>
* glsl: Validate vertex emission in geometry shaders.Iago Toral Quiroga2014-06-301-14/+134
| | | | | | | Check if non-zero streams are used. Fail to link if emitting to unsupported streams or emitting to non-zero streams with output type other than GL_POINTS. Reviewed-by: Chris Forbes <[email protected]>
* glsl: Add support for EmitStreamVertex() and EndStreamPrimitive().Iago Toral Quiroga2014-06-301-0/+58
| | | | Reviewed-by: Chris Forbes <[email protected]>
* glsl: Modify ir_end_primitive to have a stream.Iago Toral Quiroga2014-06-307-16/+64
| | | | | | | This will be necessary to implement EndStreamPrimitive(). EndPrimitive() will produce an ir_end_primitive with the default stream 0. Reviewed-by: Chris Forbes <[email protected]>
* glsl: Modify ir_emit_vertex to have a stream.Iago Toral Quiroga2014-06-3010-21/+68
| | | | | | | This will be necessary to implement EmitStreamVertex(). EmitVertex() will produce an ir_emit_vertex with the default stream 0. Reviewed-by: Chris Forbes <[email protected]>
* i965/gs: Set number of control data bits for stream mode.Iago Toral Quiroga2014-06-301-4/+5
| | | | | | | | | If the geometry shader is indeed using streams then we need 2 control data bits per vertex for the StreamID. If the shader is not using streams then we don't need control data bits. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Store info about geometry shaders that emit vertices to non-zero streams.Iago Toral Quiroga2014-06-304-0/+5
| | | | | | | | | | | On Intel hardware when a geometry shader outputs GL_POINTS primitives we only need to emit vertex control bits if it emits vertices to non-zero streams, so use a flag to track this. This flag will be set to TRUE when a geometry shader calls EmitStreamVertex() or EndStreamPrimitive() with a non-zero stream parameter in a later patch. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Only geometry shader outputs can be associated with non-zero streams.Iago Toral Quiroga2014-06-301-0/+5
| | | | | | | This should be ensured by the parser, so assert on that. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Two varyings can't write to the same buffer from different streams.Iago Toral Quiroga2014-06-301-0/+17
| | | | | | | If this is detected, fail to link. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Add methods to retrive a varying's name and streamId.Iago Toral Quiroga2014-06-301-0/+10
| | | | | Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Fail to link if inter-stage input/outputs are not assigned to stream 0Iago Toral Quiroga2014-06-301-0/+8
| | | | | | | Outputs that are linked to inputs in the next stage must be output to stream 0, otherwise we should fail to link. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Assign GLSL StreamIds to transform feedback outputs.Iago Toral Quiroga2014-06-302-3/+16
| | | | | | Inter-shader outputs must be on stream 0, which is the default. Reviewed-by: Chris Forbes <[email protected]>
* i965: Enable transform feedback for streams > 0Iago Toral Quiroga2014-06-301-24/+43
| | | | | | | Configure hardware to read vertex data for all streams and have all streams write their varyings to the corresponsing output buffers. Reviewed-by: Ian Romanick <[email protected]>
* mesa: add StreamId information to transform feedback outputs.Iago Toral Quiroga2014-06-302-0/+2
| | | | | | | For now initialized to the default stream 0. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Add parsing support for multi-stream output in geometry shaders.Samuel Iglesias Gonsalvez2014-06-307-1/+144
| | | | | | | | This implements parsing requirements for multi-stream support in geometry shaders as defined in ARB_gpu_shader5. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* st/omx: strcpy the string into the allocated bufferEmil Velikov2014-06-281-3/+3
| | | | | | | | | | This fixes commit a001ca98e15(st/omx: keep the name, (name|role)_specific strings dynamically allocated) in which we dynamically allocated the buffers for name and (name|role)_specific yet forgot to copy the encoder strings into them. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80614 Signed-off-by: Emil Velikov <[email protected]>
* mesa: expose ARB_seamless_cubemap_per_texture when supportedIlia Mirkin2014-06-282-0/+2
| | | | | | | | All of the bits appear to already be in place to support this in the sampler (which the original AMD version didn't allow). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/omx: keep the name, (name|role)_specific strings dynamically allocatedEmil Velikov2014-06-272-9/+52
| | | | | | | | | | ... as it's caller (the external program omxregister-bellagio) is the one who frees all of the allocated memory. Reported-by: Pedretti Fabio <[email protected]> Tested-by: Fabio Pedretti <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Christian König <[email protected]>
* docs: Update the status of a few things in GL3.txtChris Forbes2014-06-271-8/+8
| | | | Signed-off-by: Chris Forbes <[email protected]>
* nv50: fix dri3 prime buffer creationAxel Davy2014-06-271-2/+6
| | | | | | | | | This is the same fix than "nvc0: fix dri3 prime buffer creation" Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nvc0: fix dri3 prime buffer creationDave Airlie2014-06-271-1/+1
| | | | | | | | We need to place shared buffers into GART. Reviewed-by: Axel Davy <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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