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* ac/nir: Add merged GS function.Bas Nieuwenhuizen2017-10-201-17/+63
* radv: Only emit TES when it exists.Bas Nieuwenhuizen2017-10-201-4/+6
* radv: Use control shader presence for detecting tess.Bas Nieuwenhuizen2017-10-201-1/+1
* radv: fixup tess eval shader when combined.Dave Airlie2017-10-202-6/+23
* radv: Set VGT_GS_MODE properly for gfx9Bas Nieuwenhuizen2017-10-201-4/+7
* radv: ensure correct outinfo is picked.Dave Airlie2017-10-201-13/+14
* swr: Rework scratch space allocationGeorge Kyriazis2017-10-192-30/+23
* radv: Enable tessellation shaders for GFX9.Bas Nieuwenhuizen2017-10-201-1/+1
* ac/nir: init full exec mask for merged shaders.Dave Airlie2017-10-203-0/+12
* radv: drop unused r600_htile_info.Dave Airlie2017-10-201-9/+0
* radv: fix CLEAR_STATE packet length.Dave Airlie2017-10-191-1/+1
* meson: don't build gallium dri target if gallium is disabledDylan Baker2017-10-191-1/+1
* radv: copy indirect lowering settings from radeonsiTimothy Arceri2017-10-201-1/+26
* radv: stop redundant setting of active_stagesTimothy Arceri2017-10-201-2/+0
* ac: move some code out of loop in store_tcs_output()Timothy Arceri2017-10-201-5/+5
* radv: Modify rsrc1/rsrc2 generation for merged tess.Bas Nieuwenhuizen2017-10-191-7/+16
* radv: Set correct registers for merged shader rings.Bas Nieuwenhuizen2017-10-191-12/+24
* radv: Add GFX9 HS emitting code.Bas Nieuwenhuizen2017-10-191-5/+16
* radv: Remove remaining hard coded references to VS.Bas Nieuwenhuizen2017-10-193-7/+28
* radv: Update GFX9 user data regs for GS/tess.Bas Nieuwenhuizen2017-10-194-14/+25
* radv: Add code to compile merged shaders.Bas Nieuwenhuizen2017-10-194-13/+39
* ac/nir: Add LS-HS input VGPR workaround.Bas Nieuwenhuizen2017-10-191-0/+18
* ac/nir: Compile the bodies of multiple shaders.Bas Nieuwenhuizen2017-10-191-50/+83
* ac/nir: Expand user SGPR descriptions a bit.Bas Nieuwenhuizen2017-10-191-3/+3
* ac/nir: Don't write to the dynamic HS word on GFX9.Bas Nieuwenhuizen2017-10-191-11/+16
* ac/nir: Add function creation for merged LS+HS.Bas Nieuwenhuizen2017-10-191-76/+178
* ac/nir: Make scan_shader_output_decl less dependent on the context.Bas Nieuwenhuizen2017-10-191-14/+17
* ac/nir: Allow ac_shader_variant_info to contain info about multiple stages.Bas Nieuwenhuizen2017-10-191-1/+1
* ac/nir: Change interface to allow multiple source shaders.Bas Nieuwenhuizen2017-10-193-39/+48
* ac/nir: Add HS calling convention.Bas Nieuwenhuizen2017-10-191-1/+4
* ac: Parse the new HS RSRC1 register.Bas Nieuwenhuizen2017-10-191-0/+1
* swr: knob overrides for Intel Xeon PhiTim Rowley2017-10-195-1/+37
* swr/rast: Add api to override draws in flightTim Rowley2017-10-194-19/+31
* swr/rast: Widen fetch shader to SIMD16 (disabled for now)Tim Rowley2017-10-191-13/+428
* swr/rast: Change DS memory allocationTim Rowley2017-10-192-2/+3
* swr/rast: Fix indentationTim Rowley2017-10-191-1/+1
* swr/rast: Miscellaneous viewport array code changesTim Rowley2017-10-195-38/+71
* swr/rast: Minor changes for os-xTim Rowley2017-10-191-2/+4
* i965: Don't disable aux buffers for non-overlapping miplevels.Kenneth Graunke2017-10-191-3/+7
* i965: Remove the intel_miptree_prepare_fb_fetch wrapper.Kenneth Graunke2017-10-193-20/+10
* i965: Only resolve texture levels/layers that are accessed.Kenneth Graunke2017-10-191-2/+16
* i965: Make intel_miptree_prepare_texture() take level/layer arguments.Kenneth Graunke2017-10-193-21/+13
* gallium: add more exceptions to tgsi_util_get_inst_usage_maskTim Rowley2017-10-191-0/+12
* isl: Fix width check in isl_gen7_choose_msaa_layout.Kenneth Graunke2017-10-191-1/+1
* i965: Use is_scheduling_barrier instead of schedule_node::is_barrier.Kenneth Graunke2017-10-191-22/+10
* i965: Move fs_inst::has_side_effects()'s eot check to the parent class.Kenneth Graunke2017-10-195-9/+3
* tgsi: fix tgsi_util_get_inst_usage_maskRoland Scheidegger2017-10-191-6/+6
* docs: update calendar, add news item and link release notes for 17.2.3Emil Velikov2017-10-193-7/+8
* docs: add sha256 checksums for 17.2.3Emil Velikov2017-10-191-1/+2
* docs: add release notes for 17.2.3Emil Velikov2017-10-191-0/+180
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