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* winsys/radeon: Only add bo to hash table when creating flinkMartin Andersson2013-03-011-4/+4
| | | | | | | | | | | | | The problem is that we mix bo handles and flinked names in the hash table. Because kms type handles are not flinked they should not be added to the hash table. If we do that we will sooner or later get a situation where we will overwrite a correct entry because the bo handle was the same as a flinked name. Note: this is a candidate for the stable branches. Reviewed-by: Jerome Glisse <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* i965: enable ARB_texture_multisample on Gen6+Chris Forbes2013-03-021-0/+1
| | | | | | | | V2: Works on Ivy Bridge now too, so this can be 6+. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: add support for ir_txf_ms on Gen6+Chris Forbes2013-03-023-13/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | On Gen6, lower this to `ld` with lod=0 and an extra sample_index parameter. On Gen7, use `ld2dms`. We don't support CMS yet for multisample textures, so we just hardcode MCS=0. This is ignored for IMS and UMS surfaces. Note: If we do end up emitting specialized shaders based on the MSAA layout, we can emit a slightly shorter message here in the UMS case. Note: According to the PRM, `ld2dms` takes one more parameter, lod. However, it's always zero, and including it would make the message too long for SIMD16, so we just omit it. V2: Reworked completely, added support for Gen7. V3: - Introduce sample_index parameter rather than reusing lod - Removed spurious whitespace change - Clarify commit message V4: - Fix comment style - Emit SHADER_OPCODE_TXF_MS on Gen6. This was benignly wrong since it lowers to `ld` anyway on this gen, but still wrong. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vs: add support for ir_txf_ms on Gen6+Chris Forbes2013-03-021-4/+21
| | | | | | | | | | | | | | | | | | On Gen6, lower this to `ld` with lod=0 and an extra sample_index parameter. On Gen7, use `ld2dms`. This takes an additional MCS parameter to support compressed multisample surfaces, but we're not enabling them for multisample textures for now, so it's always ignored and can be safely omitted. V2: Reworked completely, added support for Gen7. V3: - Use new sample_index, sample_index_type rather than reusing lod - Clarify commit message. V4: - Fix comment style Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: add a new virtual opcode: SHADER_OPCODE_TXF_MSChris Forbes2013-03-025-0/+18
| | | | | | | | | | | | | This is very similar to the TXF opcode, but lowers to `ld2dms` rather than `ld` on Gen7. V4: - add SHADER_OPCODE_TXF_MS to is_tex() functions, so regalloc thinks it actually writes the correct number of registers. Otherwise in nontrivial shaders some of the registers tend to get clobbered, producing bad results. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: take the target into account for Gen7 MSAA modesChris Forbes2013-03-021-3/+19
| | | | | | | | | | | | | | | | | | | | | Gen7 has an erratum affecting the ld_mcs message, making it unsafe to use when the surface doesn't have an associated MCS. From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"): "If this field is disabled and the sampling engine <ld_mcs> message is issued on this surface, the MCS surface may be accessed. Software must ensure that the surface is defined to avoid GTT errors." To allow the shader to treat all surfaces uniformly, force UMS if the surface is to be used as a multisample texture, even if CMS would have been possible. V3: - Quoted erratum text Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Support multisampling in surface_state for texturesChris Forbes2013-03-022-5/+6
| | | | | | | | | | | | | | | | | | | The surface_state setup for renderbuffers already worked; only the texturing side needed work. BLORP does something similar, but does its own surface_state setup. On Gen6, we just need to set the correct sample count. On Gen7: - set the correct sample count - set the correct layout mode - set GEN7_SURFACE_ARYSPC_LOD0 if it's set in the miptree. V2: - Clarify commit message - Rebased onto Paul's physical/logical dims cleanup - Added Gen7 support Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: add support for multisample texturesChris Forbes2013-03-026-7/+55
| | | | | | | | | | | V2: - Fix for state moving from texobj to image - Rebased onto Paul's logical/physical cleanup - Fixed missing quantization of sample count - Fold in IMS renderbuffer wrapper fixes from later in the series - Use correct physical slice offset for UMS/CMS surfaces on Gen7 Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* mesa: implement TexImage*MultisampleChris Forbes2013-03-021-4/+163
| | | | | | | | | | | | | | | | V2: - fix formatting issues - generate GL_OUT_OF_MEMORY if teximage cannot be allocated - fix for state moving from texobj to image V3: - remove ridiculous stencil hack - alter format check to not allow a base format of STENCIL_INDEX - allow width/height/depth to be zero, to deallocate the texture - dont forget to call _mesa_update_fbo_texture V4: - fix indentation - don't throw errors on proxy texture targets Signed-off-by: Chris Forbes <[email protected]>
* mesa: support multisample textures in framebuffer completeness checkChris Forbes2013-03-021-14/+37
| | | | | | | | | | | | | | | | | | | | | | | - sample count must be the same on all attachments - fixedsamplepositions must be the same on all attachments (renderbuffers have fixedsamplepositions=true implicitly; only multisample textures can choose to have it false) V2: - fix wrapping to 80 columns, debug message, fix for state moving from texobj to image. - stencil texturing tweaks tidied up and folded in here. V3: - Removed silly stencil hacks entirely; the extension doesn't actually make stencil-only textures legal at all. - Moved sample count / fixed sample locations checks into existing attachment-type-specific blocks, as suggested by Eric V4: - Removed stencil hacks which were missed in V3 (thanks Eric) - Don't move the declaration of texImg; only required pre-V3. Signed-off-by: Chris Forbes <[email protected]> [V2] Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: expose sample positionsChris Forbes2013-03-023-43/+82
| | | | | | | | | | | | Moves the definition of the sample positions out of gen6_emit_3dstate_multisample, and unpacks them in gen6_get_sample_position. V2: Be consistent about `sample position` rather than `location`. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Acked-by: Ian Romanick <[email protected]>
* i965: add support for sample mask on Gen6+Chris Forbes2013-03-024-9/+16
| | | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: implement sample maskChris Forbes2013-03-025-2/+53
| | | | | | | | | | | | | | | | V2: - fix multiline comment style - stop using ASSERT_OUTSIDE_BEGIN_END_AND_FLUSH since that doesn't exist anymore. V3: - check for the extension being enabled - tidier flagging of _NEW_MULTISAMPLE - fix weird indentation in get.c V4: - move flush later in SampleMaski() Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: implement GetMultisamplefvChris Forbes2013-03-023-2/+34
| | | | | | | | | | | | | | | Actual sample locations deferred to a driverfunc since only the driver really knows where they will be. V2: - pass the draw buffer to the driverfunc; don't fallback to pixel center if driverfunc is missing. - rename GetSampleLocation to GetSamplePosition - invert y sample position for winsys FBOs, at Paul's suggestion Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: expose new max sample countsChris Forbes2013-03-021-2/+10
| | | | | | | | | | V2: For now, only expose a depth sample count of 1, since there are possible unresolved interactions with HiZ. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: add new max sample count stateChris Forbes2013-03-023-0/+13
| | | | | | | | | | | | | | - GL_MAX_COLOR_TEXTURE_SAMPLES - GL_MAX_DEPTH_TEXTURE_SAMPLES - GL_MAX_INTEGER_SAMPLES V2: initialize limits to 1 in _mesa_init_constants as suggested by Brian and Paul Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: add support for ARB_texture_multisampleChris Forbes2013-03-0220-26/+153
| | | | | | | | | | | | | | | | | | V2: - emit `sample` parameter properly for multisample texelFetch() - fix spurious whitespace change - introduce a new opcode ir_txf_ms rather than overloading the existing ir_txf further. This makes doing the right thing in the driver somewhat simpler. V3: - fix weird whitespace V4: - don't forget to include the new opcode in tex_opcode_strs[] (thanks Kenneth for spotting this) Signed-off-by: Chris Forbes <[email protected]> [V2] Reviewed-by: Eric Anholt <[email protected]> [V2] Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* tests: add ARB_texture_multisample enums to tableChris Forbes2013-03-021-0/+21
| | | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: add texobj support for ARB_texture_multisampleChris Forbes2013-03-0210-22/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the new texture targets, and per-image state for GL_TEXTURE_SAMPLES and GL_TEXTURE_FIXED_SAMPLE_LOCATIONS. V2: - Allow multisample texture targets in glInvalidateTexSubImage too. This was already partly there, but I missed it the first time around since the interaction is defined in a newer extension. Fixed weird indentation. - Allow multisample array textures in glFramebufferTextureLayer. This was overlooked as the tests originally only used 2d multisample textures. V3: - Set min/mag filters sensibly for multisample textures. This can't actually be changed by the user, so it's more sensible to initialize it correctly than to hack around it being bogus later. V4: - Tidy up initial min/mag filter setup. Setup in _mesa_initialize_texture_object was bogus, but benign since finish_texture_init() clobbered everything with correct values. For V4, just do the setup in finish_texture_init(). V5: - Don't break glPopAttrib(GL_TEXTURE_BIT) Signed-off-by: Chris Forbes <[email protected]> [V2] Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glapi: add ARB_texture_multisampleChris Forbes2013-03-027-5/+128
| | | | | | | | | | | | | | | | | | | | Adds new enums, dispatch machinery, and stubs for the 4 new entrypoints. V2: - Drop placeholder - Align enum values - Remove explicit exec=mesa; it *is* the dispatch flavor we want, but it's also the default. I misunderstood how this worked before; after actually reading the generator it makes good sense. V3: - Squash in stubs for new entrypoints, and dispatch_sanity tweaks, so we don't get build breakage between those patches. V4: - Fix various remaining whitespace issues Signed-off-by: Chris Forbes <[email protected]> [1/3 V2] Reviewed-by: Matt Turner <[email protected]> [V3] Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* intel: Use the new "ctx" local variable I just added some more.Eric Anholt2013-03-011-2/+2
| | | | Reviewed-and-tested-by: Ian Romanick <[email protected]>
* i965: Make sRGB-capable framebuffers by default.Eric Anholt2013-03-012-3/+63
| | | | | | | | | | | | | The GLX extension lets you expose visuals that explicitly guarantee you that the GL_FRAMEBUFFER_SRGB_CAPABLE flag will be set, but we can set the flag even while the visual doesn't provide the guarantee. This appears to be consistent with other implementations, as we've seen several apps now that don't require an srgb visual and assume sRGB will work without checking the GL_FRAMEBUFFER_SRGB_CAPABLE flag. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55783 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60633 Reviewed-and-tested-by: Ian Romanick <[email protected]>
* intel: Fix software copying of miptree faces for weird formats.Eric Anholt2013-03-013-61/+77
| | | | | | | | | | | Now that we have W-tiled S8, we can't just region_map and poke at bits -- there has to be some swizzling. Rely on intel_miptree_map to get that job done. This should also get the highest performance path we know of for the mapping (interesting if I get around to finishing movntdqa some day). v2: Fix stale name of the bit in a comment. Reviewed-by: Chad Versace <[email protected]>
* intel: Add a flag for miptree mapping to disable transcoding.Eric Anholt2013-03-012-4/+17
| | | | | | | | I want to reuse intel_miptree_map() to replace some region mapping that's broken for separate stencil, but doing so would result in new demands on ETC transcode that we actually don't want to happen. Reviewed-by: Chad Versace <[email protected]>
* i965: Add WARN_ONCE for depthstencil workarounds we shouldn't be hitting.Eric Anholt2013-03-012-0/+6
| | | | Reviewed-by: Chad Versace <[email protected]>
* r600g: enable CP DMA on 6xxAlex Deucher2013-03-011-1/+1
| | | | | | Tested across several 6xx parts, no piglit regressions. Signed-off-by: Alex Deucher <[email protected]>
* r600g: don't require dword alignment with CP DMA for buffer transfersMarek Olšák2013-03-015-11/+9
| | | | | | which is a leftover from the days when we used streamout to copy buffers Tested-by: Andreas Boll <[email protected]>
* r600g: always map uninitialized buffer range as unsynchronizedMarek Olšák2013-03-016-0/+45
| | | | | | | | | | Any driver can implement this simple and efficient optimization. Team Fortress 2 hits it always. The DISCARD_RANGE codepath is not even used with TF2 anymore, so we avoid a ton of useless buffer copies. Tested-by: Andreas Boll <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* gallium/util: add helper code for 1D integer rangeMarek Olšák2013-03-011-0/+89
| | | | | | | | | | Reviewed-by: Brian Paul <[email protected]> v2: cosmetic changes based on Brian's review Tested-by: Andreas Boll <[email protected]> NOTE: This is a candidate for the 9.1 branch. (the next patch depends on it)
* r600g: cleanup deprecated register tablesMarek Olšák2013-03-013-45/+14
| | | | | | These registers are either already emitted elsewhere or moved to start_cs. Tested-by: Andreas Boll <[email protected]>
* r600g: unify vgt statesMarek Olšák2013-03-015-26/+9
| | | | | | | The states were split because we thought it caused a hardlock. Now we know the hardlock was caused by something else and has since been fixed. Tested-by: Andreas Boll <[email protected]>
* r600g: flush and invalidate htile cache when appropriateMarek Olšák2013-03-016-1/+21
| | | | | | Tested-by: Andreas Boll <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* r600g: atomize streamout enablingMarek Olšák2013-03-019-87/+96
| | | | | | | | | | | | This doesn't fix any issue we know of, but there indeed is a week spot in draw_vbo where streamout can fail. After streamout is enabled, the need_cs_space call can flush the context, which causes the streamout to be disabled right after it was enabled and bad things happen. One way to fix it is to atomize the beginning part, so that no context flush can happen between streamout enabling and the first drawing. Tested-by: Andreas Boll <[email protected]>
* r600g: use async DMA with a non-zero src offsetMarek Olšák2013-03-011-1/+1
| | | | | | | | probably a typo Tested-by: Andreas Boll <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* r600g: pad the DMA CS to a multiple of 8 dwordsMarek Olšák2013-03-011-2/+14
| | | | | | Tested-by: Andreas Boll <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* intel: Enable __DRI_API_OPENGL_CORE api with dri2 contextsJordan Justen2013-02-281-0/+2
| | | | | | | | | | | | | Without this set, dri_util.c:dri2CreateContextAttribs will reject requests to create a context with __DRI_API_OPENGL_CORE. This prevents a 3.2 core profile context from being created even when MESA_GL_OVERRIDE_VERSION=3.2 is used. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: update max versions based on MESA_GL_VERSION_OVERRIDEJordan Justen2013-02-281-0/+10
| | | | | | | | | If the override is version is >= 3.1, then update the max_gl_core_version. Otherwise, update max_gl_compat_version. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa version: add _mesa_get_gl_version_overrideJordan Justen2013-02-282-27/+70
| | | | | | | | | This will allow other code to get access to the override version before a context is available. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: allow GLSL compiler version to be overridden to 1.50Jordan Justen2013-02-282-0/+3
| | | | | | | | | | | | | Although GLSL 1.50 compiler support is not available, this change will allow MESA_GLSL_VERSION_OVERRIDE=150 to be used while 1.50 support is being developed. Since no drivers claim 1.50 GLSL support, this change should only impact Mesa when MESA_GLSL_VERSION_OVERRIDE=150 is set. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Put immediate operand as src2Matt Turner2013-02-281-1/+1
| | | | | | | | Immediate operands can only be src2 in 2-source instructions. Fixes piglit failures since 0a1d145e (oops!). Spotted-by: Eric Anholt <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: Remove intel_mipmap_tree::wraps_etcChad Versace2013-02-282-21/+3
| | | | | | | | | | | | | | The field was equivalent to (etc_format != MESA_FORMAT_NONE), and therefore duplicate information. This patch removes field and replaces all references to it with `etc_format != MESA_FORMAT_NONE`. No Piglit ETC test regresses on Intel Sandybridge. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* ir_to_mesa: Translate ir_triop_lrp to OPCODE_LRP.Matt Turner2013-02-281-2/+5
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Assert that ir_triop_lrp was lowered.Matt Turner2013-02-281-0/+4
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fp: Use the LRP instruction for OPCODE_LRP.Matt Turner2013-02-281-8/+4
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use the LRP instruction for ir_triop_lrp when possible.Kenneth Graunke2013-02-287-5/+75
| | | | | | | | | | | | | | | | | | | v2 [mattst88]: - Add BRW_OPCODE_LRP to list of CSE-able expressions. - Fix op_var[] array size. - Rename arguments to emit_lrp to (x, y, a) to clear confusion. - Add LRP function to brw_fs.cpp/.h. - Corrected comment about LRP instruction arguments in emit_lrp. v3 [mattst88]: - Duplicate MAD code for LRP instead of using a function pointer. - Check for != GRF instead of == IMM in emit_lrp. - Lower LRP on gen < 6. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> 1
* i965: Add support for emitting the LRP instruction.Kenneth Graunke2013-02-284-0/+4
| | | | | | | | Like MAD, this is another three-source instruction. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* glsl: Optimize ir_triop_lrp(x, y, a) with a = 0.0f or 1.0fMatt Turner2013-02-281-0/+11
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Convert mix() to use a new ir_triop_lrp opcode.Kenneth Graunke2013-02-2811-12/+84
| | | | | | | | | | | | | | | | | | | | | | | | Many GPUs have an instruction to do linear interpolation which is more efficient than simply performing the algebra necessary (two multiplies, an add, and a subtract). Pattern matching or peepholing this is more desirable, but can be tricky. By using an opcode, we can at least make shaders which use the mix() built-in get the more efficient behavior. Currently, all consumers lower ir_triop_lrp. Subsequent patches will actually generate different code. v2 [mattst88]: - Add LRP_TO_ARITH flag to ir_to_mesa.cpp. Will be removed in a subsequent patch and ir_triop_lrp translated directly. v3 [mattst88]: - Move changes from the next patch to opt_algebraic.cpp to accept 3-src operations. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* glsl: Rework ir_reader to handle expressions with three operands.Kenneth Graunke2013-02-281-26/+19
| | | | | Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* glsl: Consolidate ir_expression constructors that use explicit types.Kenneth Graunke2013-02-282-37/+10
| | | | | | | | | | | | | | | | | | | Previously, we had separate constructors for one, two, and four operand expressions. This patch consolidates them into a single constructor which uses NULL default parameters. The unary and binary operator constructors had assertions to verify that the caller supplied the correct number of operands for the expression, but the four-operand version did not. Since get_num_operands for ir_quadop_vector returns the number of vector_elements, we can safely add that without breaking the semantics of ir_quadop_vector. This also paves the way for expressions with three operands. Currently, none can be constructed since get_num_operands() never returns 3. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
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