summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* intel/eu/validate/gen12: Don't blow up on indirect src0.Jason Ekstrand2019-10-111-1/+2
| | | | | | | They look like a NULL source if you don't look at the address mode. Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/validate/gen12: Validation fixes for SEND instruction.Francisco Jerez2019-10-111-22/+28
| | | | | | | | The following fix-up by Jordan Justen is squashed in: intel/eu/validate: gen12 send instruction doesn't have a dst type field Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/validate/gen12: Fix validation of SYNC instruction.Francisco Jerez2019-10-111-1/+1
| | | | | | | src0 will typically be null for this instruction. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/validate/gen12: Implement integer multiply restrictions in EU ↵Francisco Jerez2019-10-111-0/+33
| | | | | | | | validator. Due to hardware bug filed as HSDES#1604601757. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Lower fpow on Gen12.Jordan Justen2019-10-111-0/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs/gen12: Don't support source mods for 32x16 integer multiply.Francisco Jerez2019-10-111-0/+18
| | | | | | | | | | Due to hardware bug filed as HSDES#1604601757. v2: Only return if result of fs_inst::can_do_source_mods() is known to be false for the case new orthogonal restrictions are implemented below in the future. (Caio) Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/disasm: Disassemble register file of split SEND sources.Francisco Jerez2019-10-111-1/+4
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/disasm: Don't disassemble saturate control on SEND instructions.Francisco Jerez2019-10-111-2/+4
| | | | | | | The field is gone on Gen12+ and it was illegal on previous generations. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/disasm/gen12: Disassemble Gen12 SEND instructions.Francisco Jerez2019-10-111-4/+18
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/disasm/gen12: Disassemble Gen12 SYNC instruction.Francisco Jerez2019-10-111-0/+14
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/disasm/gen12: Disassemble three-source instruction source and ↵Francisco Jerez2019-10-111-13/+32
| | | | | | destination regions. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/disasm/gen12: Fix disassembly of some common instruction controls.Francisco Jerez2019-10-111-4/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/disasm/gen12: Disassemble software scoreboard information.Francisco Jerez2019-10-111-0/+16
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/fs/gen12: Demodernize software scoreboard lowering pass.Francisco Jerez2019-10-111-81/+163
| | | | | | | Kept as a separate commit in order to avoid distracting reviewers of the software scoreboard pass with memory management boilerplate. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/fs/gen12: Introduce software scoreboard lowering pass.Francisco Jerez2019-10-115-0/+946
| | | | | | | | | | | | | | | | | | | | | | Gen12+ hardware lacks the register scoreboard logic that used to guarantee data coherency between register reads and writes in previous generations. This lowering pass runs after register allocation in order to make up for it. It works by performing global dataflow analysis in order to determine the set of potential dependencies of every instruction in the shader, and then inserts any required SWSB annotations and additional SYNC instructions in order to guarantee data coherency. v2: Drop unnecessary _safe list iteration (Caio). v3: Temporarily workaround potential WaR hazard between FPU instruction and subsequent out-of-order write, pending clarification from the hardware team. Drop redundant tracking of implicit access of acc0-1, since the hardware guarantees coherency of these (but not the other accumulators...). Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/fs/gen12: Add scheduling information to the IR.Francisco Jerez2019-10-112-0/+3
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/eu/gen12: Set SWSB annotations in hand-crafted assembly.Francisco Jerez2019-10-112-5/+91
| | | | | | | | | | | | | Reviewers are encouraged to audit the code generation pass independently for the case I missed some potential data hazard or new code has been added in the meantime. v2: Add SYNC instruction to cr0 workaround in brw_float_controls_mode(). v3: Drop likely redundant (and potentially harmful) RegDist SWSB annotation from ce0 read in brw_find_live_channel() (Caio). Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/eu/gen12: Add tracking of default SWSB state to the current ↵Francisco Jerez2019-10-113-0/+18
| | | | | | brw_codegen instruction. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.Francisco Jerez2019-10-111-0/+148
| | | | | | v2: Introduce extra tgl_swsb_sbid() constructor (Caio). Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/fs/gen12: Add codegen support for the SYNC instruction.Francisco Jerez2019-10-114-3/+19
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/ir/gen12: Add SYNC hardware instruction.Francisco Jerez2019-10-113-0/+3
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Don't set thread control, it's gone.Francisco Jerez2019-10-111-2/+4
| | | | | | | | An effect similar to the one formerly provided by setting thread control to "switch" can be achieved now by setting a RegDist of 1 on the SWSB field. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Don't set DD control, it's gone.Francisco Jerez2019-10-112-6/+12
| | | | | | | | A future lowering pass will simulate the same behavior originally provided by NoDDChk/NoDDClr at the IR level by using appropriate SWSB annotations. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Use SEND instruction for split sends.Francisco Jerez2019-10-112-2/+3
| | | | | | | The new SEND instruction behaves like the former SENDS instruction. The original single-payload SEND instruction is gone. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Codegen SEND descriptor regions correctly.Francisco Jerez2019-10-112-6/+14
| | | | | | | | The SEND instruction is now four-source. The descriptor is no longer part of source 1, so avoid touching it to avoid corruption while initializing the descriptor. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Codegen pathological SEND source and destination regions.Francisco Jerez2019-10-111-7/+39
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Codegen control flow instructions correctly.Francisco Jerez2019-10-111-6/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Codegen three-source instruction source and destination regions.Francisco Jerez2019-10-112-24/+42
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Fix codegen of immediate source regions.Francisco Jerez2019-10-111-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Add Gen12 opcode descriptions to the table.Francisco Jerez2019-10-111-24/+47
| | | | | | | | | | Quite a lot of churn because the encoding of most hardware opcodes has changed unfortunately. v2: Split dot-product description fixes to separate patch (Caio). Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen11+: Mark dot product opcodes as unsupported on opcode_descs table.Francisco Jerez2019-10-111-4/+4
| | | | | | These instructions have been removed from the hardware. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/eu/gen12: Implement datatype binary encoding.Francisco Jerez2019-10-111-7/+55
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Implement immediate 64 bit constant encoding.Sagar Ghuge2019-10-111-2/+13
| | | | | | | | | | | | On Gen12, 64 bit immediate constants are loaded in reverse order. Lower 32 bit gets loaded from bit 96-127 and higher 32 bits from 64-95 in instruction encoding. Signed-off-by: Sagar Ghuge <[email protected]> Co-authored-by: Matt Turner <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/eu/gen12: Implement compact instruction binary encoding.Francisco Jerez2019-10-111-39/+49
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/eu/gen12: Implement indirect region binary encoding.Francisco Jerez2019-10-111-8/+15
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/eu/gen12: Implement SEND instruction binary encoding.Francisco Jerez2019-10-111-69/+135
| | | | | | | | | v2: Fix off-by-one upper GET_BITS() bound, combine 25-29 and 30-31 descriptor fields (Ken). Shorten name of GEN12_MD() macro, drop some removed TS message descriptor fields (Jordan). Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Implement control flow instruction binary encoding.Francisco Jerez2019-10-111-0/+6
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Implement three-source instruction binary encoding.Francisco Jerez2019-10-111-67/+85
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Implement basic instruction binary encoding.Francisco Jerez2019-10-111-47/+51
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Add sanity-check asserts to brw_inst_bits() and ↵Francisco Jerez2019-10-111-0/+2
| | | | | | | | | | brw_inst_set_bits(). These caught a few bugs during the development of this series. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu/gen12: Extend brw_inst.h macros for Gen12 support.Francisco Jerez2019-10-111-202/+346
| | | | | | | | | | | | | | | | The encoding of almost every instruction field has changed in Gen12, so this involves adding a Gen12+ bitfield spec to every brw_inst macro. In addition some new macros are required to handle certain discontiguous and variable-length fields. This commit doesn't actually include the Gen12 updated bitfield specs, only the macros are extended here for reviewability. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> v2: Rename FDC() to FFDC() and FDC1() to FDC() for consistency with the existing F() and FF() macros.
* intel/ir: Represent physical edge of unconditional CONTINUE instruction.Francisco Jerez2019-10-111-0/+2
| | | | | | | | | | This edge doesn't exist in the original scalar program, but it represents a potential control flow path the EU will take in cases where control flow isn't uniform across channels of the same SIMD thread. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Represent physical edge of ELSE instruction.Francisco Jerez2019-10-111-0/+1
| | | | | | | | | | This edge doesn't exist in the original scalar program, but it represents a potential control flow path the EU will take in cases where the condition isn't uniform across channels of the same SIMD thread. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Represent logical edge of BREAK instruction.Francisco Jerez2019-10-111-0/+1
| | | | | | | | | | Currently only the physical back-edge is represented, which incidentally also leads to the exit block of the loop, but we need the direct logical edge in addition for our logical CFG representation to be complete. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Add helper function to push block onto CFG analysis stack.Francisco Jerez2019-10-111-4/+13
| | | | | Requested-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Represent physical and logical subsets of the CFG.Francisco Jerez2019-10-113-40/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This represents two control flow graphs in the same cfg_t data structure: The physical CFG that will include all possible control flow paths the EU can physically take, and the logical CFG restricted to the control flow paths that exist in the original scalar program. The latter is a subset of the former because in case of divergence the SIMD vectorized program will take control flow paths that aren't part of the original scalar program. The bblock_link constructor and bblock_t::add_successor() now take a "kind" parameter that specifies whether the edge is purely physical or whether it's part of both the logical and physical CFGs (a logical edge is of course always guaranteed to be in the physical CFG as well). bblock_t::is_predecessor_of() and ::is_successor_of() also take a kind parameter specifying which CFG is being queried. The '~>' notation will be used now in order to represent purely physical edges in IR dumps. This commit doesn't actually add nor remove any edges from the CFG (the only edges marked as purely physical here are the two WHILE loop ones that already existed). Optimization passes should continue using the same (incomplete) physical CFG they were using before until they're fixed to do something smarter in a later commit, so this shouldn't lead to any functional changes. v2: Remove tabs from lines changed in this file (Caio). Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Drop hard-coded correspondence between IR and HW opcodes.Francisco Jerez2019-10-112-95/+85
| | | | | | | | | | | | | Having the IR opcodes locked to their hardware representation is risky because it causes opcodes as different as BRC and IFF to compare equal at the IR level (luckily the back-end only ever uses one opcode from each group, right now), and it prevents us from supporting instructions that change their hardware representation across generations, which will become a problem on Gen12+ platforms. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.Francisco Jerez2019-10-117-15/+41
| | | | | | | | | | | | Change brw_inst_set_opcode() and brw_inst_opcode() to call brw_opcode_encode/decode() transparently in order to translate between hardware and IR opcodes, and update the EU compaction code in order to do the same as needed, so we can eventually drop the one-to-one correspondence between hardware and IR opcodes. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Rework opcode description tables to allow efficient look-up by ↵Francisco Jerez2019-10-115-304/+166
| | | | | | | | | | | | | | | | | | | | either HW or IR opcode. This rewrites the current opcode description tables as a more compact flat data structure. The purpose is to allow efficient constant-time look-up by either HW or IR opcode, which will allow us to drop the hard-coded correspondence between HW and IR opcodes -- See the next commits for the rationale. brw_eu.c is now built as C++ source so we can take advantage of pointers to member in order to make the look-up function work regardless of the opcode_desc member used as look-up key. v2: Optimize devinfo struct comparison (Caio) Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Fix up various type conversions in brw_eu.c that are illegal C++.Francisco Jerez2019-10-114-13/+13
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 05:56:06 +0000