| Commit message (Expand) | Author | Age | Files | Lines |
... | |
* | nir/algebraic: Replace a pattern where iand with a Boolean is used as a bcsel | Ian Romanick | 2019-04-18 | 1 | -0/+4 |
* | nir/algebraic: Recognize open-coded copysign(1.0, a) | Ian Romanick | 2019-04-18 | 1 | -0/+6 |
* | intel/fs: Generate better code for fsign multiplied by a value | Ian Romanick | 2019-04-18 | 1 | -0/+43 |
* | intel/fs: Add a scale factor to emit_fsign | Ian Romanick | 2019-04-18 | 2 | -12/+77 |
* | intel/fs: Refactor code generation for nir_op_fsign to its own function | Ian Romanick | 2019-04-18 | 2 | -65/+65 |
* | intel/fs: Eliminate dead code first | Ian Romanick | 2019-04-18 | 1 | -0/+8 |
* | freedreno: Fix format string warning | Kristian H. Kristensen | 2019-04-18 | 1 | -1/+1 |
* | freedreno/a6xx: Add helper for incrementing regid | Kristian H. Kristensen | 2019-04-18 | 1 | -1/+10 |
* | freedreno: Use enum values from matching enum | Kristian H. Kristensen | 2019-04-18 | 2 | -3/+3 |
* | freedreno/a2xx: Fix redundant if statement | Kristian H. Kristensen | 2019-04-18 | 1 | -16/+14 |
* | freedreno/ir3: Mark ir3_context_error() as NORETURN | Kristian H. Kristensen | 2019-04-18 | 2 | -3/+3 |
* | nir: Add a nir_src_as_intrinsic() helper | Jason Ekstrand | 2019-04-18 | 5 | -51/+19 |
* | nir: Rework nir_src_as_alu_instr to not take a pointer | Jason Ekstrand | 2019-04-18 | 4 | -26/+18 |
* | nir: Drop "struct" from some nir_* declarations | Jason Ekstrand | 2019-04-18 | 3 | -11/+11 |
* | anv: implement WaEnableStateCacheRedirectToCS | Lionel Landwerlin | 2019-04-18 | 1 | -0/+11 |
* | i965: implement WaEnableStateCacheRedirectToCS | Lionel Landwerlin | 2019-04-18 | 2 | -0/+6 |
* | iris: implement WaEnableStateCacheRedirectToCS | Lionel Landwerlin | 2019-04-18 | 2 | -0/+12 |
* | anv/device: expose VK_KHR_shader_float16_int8 in gen8+ | Iago Toral Quiroga | 2019-04-18 | 2 | -0/+10 |
* | anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+2 |
* | compiler/spirv: move the check for Int8 capability | Iago Toral Quiroga | 2019-04-18 | 1 | -4/+3 |
* | intel/compiler: validate region restrictions for mixed float mode | Iago Toral Quiroga | 2019-04-18 | 2 | -0/+880 |
* | intel/compiler: validate conversions between 64-bit and 8-bit types | Iago Toral Quiroga | 2019-04-18 | 2 | -0/+105 |
* | intel/compiler: validate region restrictions for half-float conversions | Iago Toral Quiroga | 2019-04-18 | 2 | -1/+270 |
* | intel/compiler: also set F execution type for mixed float mode in BDW | Iago Toral Quiroga | 2019-04-18 | 1 | -16/+20 |
* | intel/compiler: implement SIMD16 restrictions for mixed-float instructions | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+72 |
* | intel/compiler: skip MAD algebraic optimization for half-float or mixed mode | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+4 |
* | intel/compiler: remove inexact algebraic optimizations from the backend | Iago Toral Quiroga | 2019-04-18 | 1 | -38/+1 |
* | intel/compiler: fix cmod propagation for non 32-bit types | Iago Toral Quiroga | 2019-04-18 | 1 | -4/+9 |
* | intel/compiler: add a brw_reg_type_is_integer helper | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+18 |
* | intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+26 |
* | intel/compiler: generalize the combine constants pass | Iago Toral Quiroga | 2019-04-18 | 1 | -22/+212 |
* | intel/eu: force stride of 2 on NULL register for Byte instructions | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+11 |
* | intel/compiler: ask for an integer type if requesting an 8-bit type | Iago Toral Quiroga | 2019-04-18 | 1 | -2/+3 |
* | intel/compiler: rework conversion opcodes | Iago Toral Quiroga | 2019-04-18 | 1 | -19/+22 |
* | intel/compiler: activate 16-bit bit-size lowerings also for 8-bit | Iago Toral Quiroga | 2019-04-18 | 1 | -1/+1 |
* | intel/compiler: split is_partial_write() into two variants | Iago Toral Quiroga | 2019-04-18 | 11 | -30/+54 |
* | intel/compiler: workaround for SIMD8 half-float MAD in gen8 | Iago Toral Quiroga | 2019-04-18 | 1 | -11/+28 |
* | intel/compiler: fix ddy for half-float in Broadwell | Iago Toral Quiroga | 2019-04-18 | 1 | -2/+15 |
* | intel/compiler: fix ddx and ddy for 16-bit float | Iago Toral Quiroga | 2019-04-18 | 1 | -19/+18 |
* | intel/compiler: set correct precision fields for 3-source float instructions | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+16 |
* | intel/compiler: allow half-float on 3-source instructions since gen8 | Iago Toral Quiroga | 2019-04-18 | 1 | -1/+2 |
* | intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits | Iago Toral Quiroga | 2019-04-18 | 1 | -1/+4 |
* | intel/compiler: add new half-float register type for 3-src instructions | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+4 |
* | intel/compiler: add instruction setters for Src1Type and Src2Type. | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+2 |
* | intel/compiler: drop unnecessary temporary from 32-bit fsign implementation | Iago Toral Quiroga | 2019-04-18 | 1 | -3/+2 |
* | intel/compiler: implement 16-bit fsign | Iago Toral Quiroga | 2019-04-18 | 1 | -1/+16 |
* | intel/compiler: handle extended math restrictions for half-float | Iago Toral Quiroga | 2019-04-18 | 3 | -12/+34 |
* | intel/compiler: lower some 16-bit float operations to 32-bit | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+5 |
* | intel/compiler: assert restrictions on conversions to half-float | Iago Toral Quiroga | 2019-04-18 | 1 | -2/+3 |
* | intel/compiler: handle b2i/b2f with other integer conversion opcodes | Iago Toral Quiroga | 2019-04-18 | 1 | -8/+8 |